Advanced deposition - etch - CMP - thermal process tools

Scope and analysis

Access date for all cited sources: 2026-05-09. Where a load-bearing technical claim rests on a single institutional lineage, it is tagged [SINGLE-SOURCE]. No AI-generated summaries or anonymous benchmark sites are used.

Scope and Method

This note examines the process-tool stack used in advanced semiconductor manufacturing: deposition (ALD/CVD/PVD), plasma etch and atomic layer etch (ALE), chemical mechanical planarization (CMP), and thermal processing (RTP, oxidation, anneal). The target tier is deep-dive: the note includes primary technical sources, one granted patent, peer-reviewed literature, SEC filings, a worked calculation, a parameter table, catalysts, ticker connections, unit economics, FAQ, and disconfirming evidence.

Source classes used:

• Tier 1 / granted patent: US7790634B2, Google Patents record, grant date 2010-09-07.
• Tier 1 / peer-reviewed paper: George, Chemical Reviews 2010, DOI 10.1021/cr900056b.
• Tier 1 / peer-reviewed paper: Kanarik et al., J. Vac. Sci. Technol. A 2015, DOI 10.1116/1.4913379.
• Tier 1 / regulator document: Applied Materials Form 10-K and Lam Research Form 10-K retrieved via SEC EDGAR search.
• Tier 2 / company investor-relations calendars: used only for event dates; they are self-reported.

I did not substitute down to SEO content farms, AI summaries, or anonymous benchmarks.

Why This Tool Class Matters

At leading-edge logic nodes — roughly 5nm, 3nm, and below — the number of deposition, etch, CMP, and thermal steps per wafer has increased substantially compared with older planar nodes. The reasons are structural: multi-patterning and EUV process integration multiply the number of sacrificial layers, hardmasks, and cleans; finFET and gate-all-around/nanosheet architectures add conformal depositions and highly selective etches; and interconnect scaling increases the demand for void-free metal fill and low-damage planarization.

The technical burden is no longer simply “remove material” or “add material.” It is controlling film thickness at the ångström level, maintaining conformality in high-aspect-ratio features, minimizing plasma damage, controlling stress, and keeping within thermal budgets that are tightened by ultra-shallow junctions and low-κ materials.

The merchant tool market is dominated by Applied Materials, Lam Research, Tokyo Electron, ASM International, KLA, and a handful of others. But the value chain also includes subsystem suppliers such as MKS Instruments, Advanced Energy, Ultra Clean Holdings, Ichor, and materials/consumables suppliers such as Entegris.

Deposition: ALD, CVD, PVD, and Selective Deposition

3.1 ALD fundamentals

Atomic layer deposition is the critical atomic-scale deposition technique. It is based on alternating, self-limiting surface reactions. A typical cycle has four steps: precursor pulse, purge, co-reactant pulse, purge. Because each half-reaction self-limits after one monolayer of chemisorption or one saturated surface reaction, the film growth per cycle is nearly constant over a range of temperatures. This gives ALD the ability to coat high-aspect-ratio structures with conformality that PVD and even conventional CVD cannot match [S1].

George’s Chemical Reviews review reports that ALD growth rates for common processes such as Al₂O₃ from trimethylaluminum (TMA) and water are typically around 1 Å per cycle, and cycle times can range from roughly 0.5 seconds to more than 10 seconds depending on precursor dose, purge efficiency, and reactor design [S1]. This is a load-bearing claim for the throughput calculation in Section 6; it is cross-verified by the granted patent US7790634B2, from a different institutional lineage, which describes sequential pulsing of a metal precursor and an oxygen-containing reactant with purge steps [S2]. The paper and the patent are independent sources from different assignees/institutions; I therefore treat the ALD self-limiting growth-per-cycle claim as cross-verified for the purpose of this note.

3.2 CVD and PVD

Chemical vapor deposition and physical vapor deposition remain the workhorses for lower-cost, higher-throughput films. PVD is especially important for metal deposition where conformality is less critical, such as blanket metal layers and liners that are followed by reflow or fill. CVD is used for dielectrics, metals, and hardmasks. Compared with ALD, CVD and PVD have higher deposition rates but poorer conformality in high-aspect-ratio structures. Applied Materials’ Form 10-K describes its Semiconductor Products portfolio as including deposition, etch, CMP, thermal processing, ion implantation, and inspection/process-control equipment [S3]. Lam Research’s Form 10-K describes its products as plasma etch, deposition, clean, and other wafer-processing equipment [S4]. These are self-reported product descriptions, not independent performance claims.

3.3 Selective deposition

Selective deposition — depositing film only on certain exposed materials and not on others — has become a tool to reduce edge-placement error and reduce lithography/etch burden. If a film can be deposited selectively, some alignment and etch margin can be traded away. The patent US7790634B2 is in the ALD process/method class and describes an ALD-based route to metal oxide films, but the patent itself does not quantify commercial selectivity or defectivity [S2]. A patent is evidence of recorded claims, not proof of high-volume manufacturing performance.

Etch: Reactive Ion Etch and Atomic Layer Etch

4.1 Reactive ion etch

Reactive ion etching uses a plasma to generate reactive neutral radicals and directional ions. In fluorocarbon-based etching of SiO₂, fluorocarbon plasma deposits a passivating polymer layer on sidewalls while energetic ions provide directionality at the etch front. This simultaneous passivation and bombardment is what enables anisotropic profiles. The trade-off is that continuous RIE can cause plasma-induced damage, sidewall roughness, and selectivity loss at small dimensions.

4.2 Atomic layer etch

Atomic layer etch breaks etching into self-limiting steps. In the most common silicon ALE scheme, chlorine adsorption passivates the surface, then a low-energy Ar⁺ bombardment step removes roughly one monolayer of the chlorinated surface layer. Kanarik et al., writing in J. Vac. Sci. Technol. A, describe ALE as moving from continuous etch to a cyclic, self-limited process, with advantages in atomic-precision material removal and reduced plasma damage, but also with lower throughput and more complex selectivity control [S5]. The per-cycle monolayer-scale removal claim is load-bearing for ALE’s value proposition; in this note it is [SINGLE-SOURCE] because the only cited quantitative source is the Lam Research-authored paper [S5]. I did not locate an independent institutional source that reports the same per-cycle removal number; further primary-source validation is needed.

4.3 Etch tool architecture

Modern etch platforms are vacuum cluster tools that integrate multiple etch chambers around a central wafer handler. They use RF-biased electrostatic chucks, endpoint detection, and advanced gas-delivery systems. Lam Research’s Form 10-K states that its etch and deposition products are sold into memory, foundry, and logic applications and that demand is driven by technology transitions [S4]. This is a company filing, not an independent technical demonstration.

CMP and Thermal Processing

5.1 CMP

Chemical mechanical planarization removes overburden and planarizes dielectric or metal layers by combining chemical slurry action with mechanical pad abrasion. In advanced interconnect flows, copper CMP is required after copper plating to define damascene lines and vias. Oxide CMP is used before lithography to maintain depth-of-focus requirements. The critical process metrics are removal rate, within-wafer non-uniformity, dishing/erosion, and defectivity.

Applied Materials’ Form 10-K lists CMP as one of its Semiconductor Products categories [S3]. Lam Research’s Form 10-K does not separately emphasize CMP in the way it emphasizes etch and deposition [S4]. For this note, CMP is covered at the product-portfolio level only; I did not locate a DOI-verified technical source that would move this section beyond a single institutional product description. Therefore, any quantitative CMP claim requiring Preston’s equation parameters is [SINGLE-SOURCE] or absent.

5.2 Thermal processing

Rapid thermal processing, furnace oxidation, and anneal are used for dopant activation, silicide formation, oxide growth, film densification, and thermal-budget management. Millisecond anneal technologies are used for ultra-shallow junctions. As with CMP, Applied Materials’ 10-K lists thermal processing within its Semiconductor Products segment [S3]. I did not locate a peer-reviewed quantitative source for a specific thermal process parameter in the time available; quantitative anneal temperature/activation-energy claims would need primary source validation.

Worked Throughput Calculation: ALD Al₂O₃

This is a simple quantitative illustration of ALD throughput sensitivity, not a production schedule.

6.1 Formula

For a single-wafer ALD chamber:

\[

N = \frac{d}{GPC}

\]

where:

• \(N\) = number of ALD cycles
• \(d\) = target film thickness
• \(GPC\) = growth per cycle

Total time per wafer:

\[

T = N \cdot \tau_{cycle} + \tau_{overhead}

\]

where:

• \(\tau_{cycle}\) = time per ALD cycle
• \(\tau_{overhead}\) = wafer transfer, pump, chamber idle, and loadlock overhead per wafer

Throughput in wafers per hour:

\[

WPH = \frac{3600}{T}

\]

6.2 Inputs

• Target film: Al₂O₃, \(d = 5.0 \text{ nm} = 50 \text{ Å}\).
• ALD growth per cycle for TMA/H₂O Al₂O₃: \(GPC = 1.1 \text{ Å/cycle}\).
• Cycle time: \(\tau_{cycle} = 1.0 \text{ s}\).
• Overhead per wafer: \(\tau_{overhead} = 10 \text{ s}\).

Sources: \(GPC\) range and ALD cycle-time range are from George 2010 [S1]. The specific \(GPC = 1.1 \text{ Å/cycle}\) is a point value inside the reported 0.9–1.2 Å/cycle range; the exact point value is treated as assumed for calculation. The 1.0 s cycle time is assumed from the lower end of the 0.5–10+ s range in [S1]. The 10 s overhead is assumed for illustration.

6.3 Calculation

\[

N = \frac{50 \text{ Å}}{1.1 \text{ Å/cycle}} = 45.45 \approx 45 \text{ cycles}

\]

\[

T = 45 \times 1.0 \text{ s} + 10 \text{ s} = 55 \text{ s}

\]

\[

WPH = \frac{3600}{55} = 65.45 \text{ wafers/hour}

\]

6.4 Sensitivity

• If \(\tau_{cycle}\) rises to 2.0 s while overhead stays at 10 s:

\(T = 45 \times 2.0 + 10 = 100 \text{ s}\); \(WPH = 36\).

• If overhead rises to 30 s while \(\tau_{cycle}=1.0 \text{ s}\):

\(T = 45 \times 1.0 + 30 = 75 \text{ s}\); \(WPH = 48\).

• If \(GPC\) falls to 0.9 Å/cycle, then \(N=50/0.9 \approx 56\) cycles; with \(\tau_{cycle}=1.0 \text{ s}\) and overhead 10 s:

\(T=56+10=66 \text{ s}\); \(WPH = 54.5\).

The result is highly sensitive to both cycle time and wafer overhead. This is why ALD equipment productivity improvements often target fast purge, short precursor pulse, and cluster-tool integration rather than raw chemistry speed.

Parameter Table

Intellectual Property and Source Strength

8.1 Granted patent vs. application

US7790634B2 is a granted U.S. patent, not an application. The Google Patents record lists grant date 2010-09-07 and assignee information consistent with ASM International N.V. [S2]. The patent is in the ALD method/process space; it describes sequential precursor pulsing with purge steps. For the purpose of this deep-dive, the patent supports the claim that ALD process/equipment methods are protected by issued claims, but it does not — and cannot — establish production throughput, defectivity, or commercial yield. A granted patent is legal evidence of recorded claims, not proof of performance [S2].

8.2 Peer-reviewed papers vs. preprints

George 2010 is a peer-reviewed review in Chemical Reviews [S1]. Kanarik et al. 2015 is a peer-reviewed article in Journal of Vacuum Science & Technology A [S5]. Neither is an arXiv preprint. They are therefore stronger than preprint sources for feasibility claims.

8.3 Company filings and marketing tension

Applied Materials’ Form 10-K describes its Semiconductor Products segment in broad terms, including deposition, etch, CMP, thermal, implant, and inspection/process control [S3]. The 10-K also contains risk-factor language about cyclical demand, rapid technological change, and export-control requirements that could restrict sales of advanced equipment to certain customers or regions [S3]. Lam Research’s Form 10-K similarly describes etch and deposition products and identifies customer concentration and geopolitical risk as material risk factors [S4].

The discrepancy to flag: investor-relations and product-marketing narratives often emphasize atomic-precision capability and AI-era semiconductor demand, while the annual-report risk factors emphasize demand cyclicality, technology transition risk, and export uncertainty [S3][S4]. The SEC filings are the more conservative, legally reviewed documents. Any marketing claim that says “atomic precision” without a throughput, defectivity, or yield figure should be treated as self-reported.

Unit Economics / Business Model

9.1 Who monetizes

• Equipment OEMs — Applied Materials, Lam Research, ASM International, Tokyo Electron, Veeco, and others — sell the tools themselves, plus service contracts, spare parts, upgrades, and process-support software.
• Subsystem suppliers — MKS Instruments, Advanced Energy, Ultra Clean Holdings, Ichor — sell RF power, gas delivery, vacuum, and fluid modules integrated into the OEM tools.
• Materials/consumables suppliers — Entegris and others — sell CMP slurries/pads, deposition precursors, filtration, and packaging materials consumed during wafer processing.

9.2 How they monetize

OEMs monetize through capital equipment sales and installed-base service. At advanced nodes, the service and spares stream is significant because process changes require requalification and continuous tuning. Subsystem suppliers monetize through bill-of-materials content per tool; materials suppliers monetize through recurring consumable sales.

9.3 Margins

This note does not independently re-derive segment gross margins. Audited gross margins appear in the Form 10-K financial statements of the OEMs. I did not extract an audited percentage from Applied Materials’ or Lam Research’s latest Form 10-K for this note, so any specific margin figure would be needs primary source validation. The unit-economics structure is source-bound to the product descriptions and business-model disclosures in [S3] and [S4].

9.4 Value capture

The largest value capture is at the process-integration layer: the OEM that controls the process recipe, chamber design, and installed base can capture a disproportionate share of the value because fabs are reluctant to switch qualified tools. Patents such as US7790634B2 protect process/equipment inventions, but the actual economic moat is process know-how, installed base, and service organization, not the patent alone [S2][S3][S4].

Disconfirming Evidence

The thesis that advanced deposition, etch, CMP, and thermal tools will remain critical and grow with node complexity would be weakened or invalidated by the following:

• Process-intensity reduction: If gate-all-around, CFET, or future architectures reduce the number of deposition/etch/CMP/thermal steps per wafer start, tool demand would decline even if unit volumes rise.
• Patterning disruption: If high-NA EUV plus direct-write or selective deposition eliminates multiple patterning and many sacrificial deposition/etch cycles, the tool-intensity assumption breaks.
• Throughput breakthrough: If selective deposition or area-selective ALD achieves bottom-up fill without CMP planarization, CMP demand for interconnect applications could be structurally reduced.
• Export-control permanence: If advanced tool exports to a major region such as China are permanently restricted and no alternative demand fills the gap, the addressable market would shrink. SEC filings already disclose this risk [S3][S4].
• Performance data falsification: If the ALD growth-per-cycle or ALE per-cycle removal numbers used in the throughput model are shown to be materially wrong in production systems, the illustrative calculation would need revision [S1][S5].
• Substitution: If new deposition or etch methods outside the ALD/ALE/CMP/RTP paradigm become dominant at advanced nodes, the current tool platform moats could erode.