InP substrates

Source discipline used in this note

Technical, materials, and intellectual-property claims are sourced to:

• Tier 1: Ioffe Physical-Technical Institute New Semiconductor Materials archive (measured semiconductor parameters), the peer-reviewed journal Semiconductor Science and Technology (DOI-verified), and a granted U.S. patent (USPTO).
• Tier 2: Company investor-relations pages and SEC EDGAR search records are used only for adoption, product positioning, and risk-factor context.
• No Tier 3 SEO, anonymous benchmark, or AI-summary sources are used.

Numbers that could not be verified from the retrieved source set are marked needs primary source validation rather than assigned a false precision.

Executive Summary

Indium phosphide (InP) is a binary III-V compound semiconductor with a direct bandgap of about 1.344 eV at 300 K and a room-temperature lattice constant of about 5.86875 Å [1]. Those two properties make InP the preferred substrate for lattice-matched InGaAsP and InGaAs epitaxial layers that emit, amplify, and detect light in the 1.3 µm and 1.55 µm fiber-optic bands. InP also offers high electron drift velocity, which supports high-speed electronic devices such as heterojunction bipolar transistors (HBTs) and high-electron-mobility transistors (HEMTs).

The substrate sits at the bottom of a deep value chain:

`

InP single-crystal boule

-> sliced/polished substrate wafer

-> epitaxial growth (MOCVD/MBE)

-> laser/EML/SOA/photodiode/PIC fabrication

-> transceiver/module integration

-> datacenter, telecom, sensing, defense end markets

`

The deep-dive below covers the materials physics, substrate manufacturing, device building blocks, IP evidence, adoption context, monetization, buyers, catalysts, and ticker exposure.

Physical Basis and Why InP Is Structurally Important

2.1 Basic semiconductor parameters

The Ioffe NSM archive documents the key parameters used throughout this note [1][2][3]:

• InP is a zincblende III-V semiconductor.
• Room-temperature bandgap: approximately 1.344 eV [1].
• Room-temperature lattice constant: 5.86875 Å [1].
• GaAs lattice constant: 5.65325 Å [2].
• InAs lattice constant: 6.0583 Å [3].
• Electron mobility in InP: the Ioffe archive lists values that are high relative to silicon, relevant to RF device speed [1]. High-frequency performance is a source-bound claim from the Ioffe data set; this note does not cite a specific untranscribed numeric mobility value without primary-source validation.
• Direct vs. indirect gap: InP has a direct bandgap, so electron-hole recombination can occur without the phonon assistance required in silicon, enabling efficient light emission [1].

Because InP is a direct-gap material, it is optically active. Silicon, by contrast, has an indirect gap and is a poor light emitter. This is the central technical reason that silicon photonics platforms still require an InP-based laser source or a separately packaged laser.

2.2 Lattice-matching arithmetic: why InP is the substrate for 1.55 µm optics

The fiber-optic loss minimum is near 1.55 µm, and the zero-dispersion point is near 1.3 µm. The alloy InGaAsP, grown on InP, can be composition-tuned to emit and absorb across both bands while remaining lattice-matched to the InP substrate. The commonly cited lattice-matched ternary is In₀.₅₃Ga₀.₄₇As. The lattice-matching condition is calculated here using Vegard's law.

Worked calculation: lattice constant and mismatch of In₀.₅₃Ga₀.₄₇As on InP

Formula:

`

a(In_x Ga_(1-x) As) = x a(InAs) + (1 - x) a(GaAs)

`

Inputs:

• a(InAs) = 6.0583 Å [3]
• a(GaAs) = 5.65325 Å [2]
• x = 0.53 for the lattice-matched In₀.₅₃Ga₀.₄₇As composition [4]
• a(InP) = 5.86875 Å [1]

Calculation:

`

a = 0.53 6.0583 + 0.47 5.65325

= 3.210899 + 2.6570275

= 5.8679265 Å

`

Mismatch f:

`

f = (a_ternary - a_InP) / a_InP

= (5.8679265 - 5.86875) / 5.86875

= -0.0008235 / 5.86875

= -0.0001403

= -0.0140%

`

This is essentially lattice-matched. A mismatch of roughly -0.014% is smaller than the typical coherent-growth threshold for thin InGaAs layers.

Sensitivity check:

If the indium fraction x is increased from 0.53 to 0.54:

`

a = 0.54 6.0583 + 0.46 5.65325

= 3.271482 + 2.600495

= 5.871977 Å

f = (5.871977 - 5.86875) / 5.86875

= 0.003227 / 5.86875

= 0.000550

= 0.0550%

`

The mismatch changes by 0.0550% - (-0.0140%) = 0.0690 percentage points for a 0.01 change in composition. That is a large sensitivity: a small stoichiometry variation during epitaxy produces a large fractional change in the lattice mismatch. This is why epitaxial growth on InP requires tight composition control.

2.3 Parameter table

Substrate Manufacturing and Material Grades

3.1 Crystal growth

Bulk InP is commonly produced by one of two high-temperature growth paths:

• Liquid Encapsulated Czochralski (LEC): used to produce large-diameter boules; the melt is capped with boric oxide to suppress phosphorus evaporation.
• Vertical Gradient Freeze (VGF): often used for lower-defect and semi-insulating material.

The Ioffe NSM archive documents the general semiconductor behavior, but bulk-crystal-growth process detail is not a primary claim in this note. The peer-reviewed Smit et al. paper describes integration technology built on 2-inch InP substrates [4]. Claiming that LEC and VGF are the current industrial routes is an established III-V fabrication fact, but this note flags the process naming as needs primary source validation if a reader requires a growth-equipment vendor or substrate-maker technical document.

3.2 Doping and electrical grade

InP substrates are sold in electrical grades that enable different device functions:

• Semi-insulating InP: typically iron (Fe)-doped to suppress free carriers, used for high-speed electronics and photonic integrated circuits where electrical isolation between devices is needed.
• n-type InP: sulfur or tin doped.
• p-type InP: zinc doped.

The doping-conductivity relationship is consistent with the Ioffe material parameters [1]. The exact Fe-doping level used by a given supplier is not independently verified in the source set; treat supplier datasheet claims as Tier 2.

3.3 Wafer diameter and substrate segregation

The Smit et al. 2014 review describes a generic InP integration platform on 2-inch wafers [4]. That is a peer-reviewed, source-bound claim. Industry commentary about a shift to 3-inch or 4-inch InP is common, but this note did not retrieve an independent metrology study or public filing that quantifies a diameter transition; therefore any claim that “4-inch InP is mainstream” would be needs primary source validation.

Device Building Blocks and Intellectual Property

4.1 What gets built on InP

InP is the substrate for the core photonic and high-speed electronic components of modern optical networks:

• Distributed feedback (DFB) lasers
• Electro-absorption modulated lasers (EMLs)
• Semiconductor optical amplifiers (SOAs)
• Mach-Zehnder modulators
• p-i-n photodiodes
• Arrayed waveguide gratings (AWGs)
• High-speed photodetectors
• HBT and HEMT RF amplifiers

The Smit et al. paper describes an InP-based generic integration technology that can combine passive and active components on the same substrate [4]. This is a peer-reviewed demonstration of feasibility, but it does not by itself prove commercial yield, reliability, or cost at datacenter volume.

4.2 Grant-level patent evidence

The value chain has formal patent protection. The following granted patent is cited as legal claim evidence:

• U.S. Patent 7,058,246 B2, “Optical communication system with photonic integrated circuits,” assigned to Infinera Corporation, granted 2006-06-06 [5].

Important source-tier caution: A granted patent is evidence of recorded legal claims, not proof of production performance, yield, reliability, or commercial viability. This note uses the patent only to establish that InP-based photonic integration was sufficiently concrete to be claimed by assignee Infinera.

4.3 Independence check

The patent [5] and the Smit et al. review [4] come from different institutions:

• Patent assignee: Infinera Corporation [5].
• Paper authors: Eindhoven University of Technology / COBRA Research Institute, among others; published in Semiconductor Science and Technology [4].

They are independent lineages. For the load-bearing claim that InP-based photonic integration is technically feasible, the peer-reviewed paper and the granted patent provide two institutionally distinct sources.

Adoption Context and Company Disclosures

5.1 Company positioning vs. filed disclosures

Public company investor-relations pages describe InP-based products and platforms:

• Lumentum Holdings Inc. describes optical communications products, including laser sources used in datacenter and telecom transceivers [6].
• Coherent Corp. describes optical materials, lasers, and photonic devices across communications and industrial markets [8].
• MACOM Technology Solutions Holdings Inc. describes high-speed analog and photonic components, including III-V-based devices [9].
• Broadcom Inc. integrates laser sources into high-bandwidth interconnect products [10].
• Applied Optoelectronics Inc. sells laser diodes and transceivers that rely on the InP material system [11].
• Intel Corp. participates in silicon photonics, which requires external or hybrid InP laser sources [12].

These are Tier 2 self-reported adoption claims. They are useful for identifying who participates in the market, but they are not independent performance verification.

5.2 Discrepancy observation

A cross-reference against SEC EDGAR records reveals a meaningful discrepancy class:

• Company investor pages tend to emphasize product capability and bandwidth leadership.
• SEC 10-K risk-factor sections, as found in the EDGAR full-text search, tend to emphasize supply-chain dependence, customer concentration, manufacturing complexity, and pricing pressure, rather than quantitative performance guarantees [14][15].

No SEC filing retrieved in this source set attaches a quantitative yield, defect-density, or reliability number to the InP-specific marketing claims. Therefore:

Performance claims from company IR pages are self-reported and not cross-verified by the retrieved 10-K risk-factor text.

Specific wafer pricing, yield, and margin claims are needs primary source validation.

This does not mean the marketing claims are false; it means the strongest independent source available in this note does not confirm them.

5.3 Source-bound claims

• 2-inch InP generic-foundry process: documented in Smit et al. 2014 [4]. Tag: [SINGLE-SOURCE] for the specific 2-inch wafer claim within this note.
• InP-based photonic integration feasible: cross-verified by [4] + [5]. Tag: cross-verified for feasibility.
• InP is the semiconductor platform for 1.55 µm emitters: supported by Ioffe bandgap/lattice data and the InP foundry paper [1][4]. Tag: cross-verified.
• Specific supplier yield/performance superiority: not verifiable from the retrieved independent sources. Tag: needs primary source validation.

Unit Economics / Business Model

6.1 Who monetizes the technology, and how

InP substrates are monetized through a sell-through value chain, not through a single subscription or royalty model:

1. Substrate producers monetize by selling sliced and polished InP wafers to epitaxial growers and device fabs. AXT is a U.S.-listed pure-play compound semiconductor substrate company [7].
2. Epitaxial/device manufacturers monetize by selling lasers, EMLs, photodiodes, SOAs, and PICs to transceiver and system makers. Lumentum, Coherent, and MACOM participate here [6][8][9].
3. Transceiver/system integrators monetize by selling optical modules and networking equipment to hyperscalers, telecom operators, and enterprise customers. Broadcom and Applied Optoelectronics participate here [10][11].
4. Silicon-photonics integrators monetize by incorporating InP laser sources into devices; Intel is an example of an end user of InP laser dies within silicon photonics [12].

6.2 Where the value is captured

The highest gross-margin step is generally the device or module design/IP step, not the raw substrate step, because substrate wafers are a critical but commodity-like input. However, the substrate remains a technological chokepoint: few vendors can produce sufficiently uniform, low-defect semi-insulating InP material.

Margin specificity limitation: The retrieved SEC EDGAR search records do not break out segment-level InP wafer gross margin [14][15]. Any specific percentage would be needs primary source validation. The public risk-factor text does confirm pricing pressure and customer concentration as material risks, which is consistent with a capital-intensive, competitively priced substrate business.

6.3 Capacity and cost economics

InP substrates are expensive relative to silicon because:

• The phosphorus vapor pressure makes crystal growth difficult.
• The material is brittle.
• Wafer diameters are smaller than silicon, so per-die area costs are less favorable.

The Smit et al. 2014 review indicates a 2-inch generic-foundry substrate [4]. Smaller wafers mean fewer optical devices per wafer for a given die size. This is a cost-bearing structural fact. The exact cost-per-device crossover versus silicon photonics or GaAs is not independently computed in this note because public die yield and pricing data were not retrieved; any crossover estimate would be needs primary source validation.

Disconfirming Evidence

The InP-substrate thesis would be materially weakened if any of the following were demonstrated by credible independent evidence:

1. Silicon photonics with direct III-V growth on silicon reaches commercial reliability and cost parity with native InP lasers. If defect-free direct heteroepitaxy of InP or InGaAs on silicon becomes high-yield at scale, the demand for discrete InP substrates in optical transceivers would fall.
2. GaAs or alternative material systems capture the 1.3/1.55 µm emission market through quantum-dot or dilute-nitride approaches at lower cost.
3. InP substrate capacity fails to scale while defect density and wafer-diameter limitations keep per-device cost too high for 800G/1.6T datacenter volume; this would push integrators toward other architectures.
4. Customer concentration or supply-chain failures materialize in SEC filings, revealing that a small number of substrate suppliers cannot meet demand or that yields are lower than implied by company IR pages [14][15].
5. Independent metrology or regulator technical assessment shows InP device reliability below the requirements of hyperscaler or telecom deployments; the current note lacks independent reliability data, so such evidence would overturn the positive adoption narrative.