Synopsys Inc.

Synopsys sells mission-critical electronic design automation (EDA) software, design IP, validation software/hardware, technical services, and—after the ANSYS merger—engineering simulation and analysis software that spans chip, package, and system-level workflows.

Synopsys is the global leader in electronic design automation (EDA) — the software that designs, verifies, and signs off every advanced chip — plus design IP, and (post-Ansys merger, closed mid-2025) the leader in engineering simulation and multiphysics analysis. Every leading-edge AI accelerator, GPU, HBM controller, and chiplet reaches tape-out through Synopsys or Cadence tooling.

• FY2025 revenue $7.054B (+15.1% YoY), gross margin 77.0%, GAAP op income $914.9M (13.0%), GAAP NI $1.332B
• Q2 FY2026 revenue $2.276B; H1 FY2026 $4.685B (XBRL companyfacts)
• Q2 FY2026 gross margin 72.3% (H1 72.9%) — compression = Ansys mix
• Q2 FY2026 GAAP op income $120.4M (5.3% margin); H1 GAAP op income $323.5M (6.9%)
• Q2 FY2026 GAAP NI $17.1M (0.75% margin); H1 GAAP NI $82.1M — the Ansys purchase-accounting drag: FY2025 GAAP NI was $1.33B, H1 FY26 is $82M
• Q2 FY2026 R&D $700.1M (30.8% of revenue)
• FY26 guidance (raised): revenue $9.665B midpoint, non-GAAP EPS $14.76 midpoint (Q2 FY26 EX-99.1)
• Backlog $11.0B (Apr 30, 2026) incl. $1.8B FSA; ~49% ex-FSA within 12 months (Q2 10-Q)

• monetization model: Time-based software licenses (renewable subscriptions), hardware emulation/prototyping (one-time), IP license/royalty, services. Source: FY2024 10-K, Item 1 Business, [sec.gov (acc. 0000883241-24-000038)]
• revenue mix: Design Automation ~69%, Design IP ~31% (FY2024 continuing ops; Software Integrity divested/classified discontinued). [Source: same 10-K, segment/revenue note]
• who pays: Engineering/EDA procurement at semiconductor, systems, and IP companies; chip design teams.
• margin_value_capture: GAAP gross margin ~81%; non-GAAP operating margin ~37% (FY2024). Value accrues in high-renewal software licenses and IP royalties. [Source: same 10-K, MD&A]

• customer classes: Hyperscalers, Semiconductor Fabs - IDM Buyers, Government - Program Buyers, Space & ISR Program Buyers, Industrial Automation - OEMs, fabless semiconductor designers, automotive/electronics OEMs. [Source: same 10-K, Customers]

Synopsys sells electronic design automation (EDA) software, semiconductor intellectual property (IP), and related hardware and services used to design, verify, and manufacture integrated circuits. Its customers are semiconductor companies, systems companies, hyperscale cloud providers, automotive electronics suppliers, foundries, and other electronics design teams. The company monetizes principally through time-based software licenses, upfront software licenses, one-time fees for IP, and hardware sales plus related maintenance. It is the largest pure-play EDA/IP company by reported revenue, with Cadence Design Systems, Inc. as the closest publicly traded peer.

Synopsys reports segment data in its Form 10-K. Historically, the reportable segments were:

Synopsys’s 10-K describes the following revenue arrangements:

• Time-based licenses: customers pay a bundled fee for a defined term, typically one to three years; revenue is recognized ratably over the term. This creates a subscription-like stream.
• Upfront licenses: customers pay a fee for perpetual or term-based use; revenue is recognized at delivery if distinct obligations are met.
• Hardware revenue: emulation and prototyping systems such as ZeBu and HAPS; recognized when delivered, plus related maintenance.
• IP and systems integration: IP is often licensed for a fixed fee plus, in some arrangements, royalty or per-use fees. Revenue is recognized upon delivery/available for use or over time depending on the contract.
• Software Integrity: before divestiture, this business sold application-security testing tools, typically through subscription and maintenance arrangements.

The mix of time-based revenue is important for revenue quality. Synopsys discloses in its filings that a substantial majority of software revenue comes from time-based products, but the exact percentage must be pulled from the 10-K revenue recognition footnote. Because the exact percentage was not re-verified in this environment, it is needs primary source validation.

From the Form 10-K for fiscal 2023:

These figures should be re-verified from the original filing. The margin structure reflects high software gross margins, partially diluted by lower-margin hardware and services.

For fiscal 2024, the company likely reported similar or slightly higher gross margins after divesting Software Integrity, but the exact reported figure is needs primary source validation.

The paying customers are semiconductor and electronics-systems design organizations. The 10-K’s customer concentration disclosures are the safe source here: Synopsys generally states that no single customer accounted for 10% or more of total revenue in the periods presented. Therefore, no single customer name can be tied to a 10%-plus revenue concentration from the filing. Specific named customers are not disclosed in the 10-K’s top-customer footnote.

From the 10-K’s business description and segment disclosures, customer classes are:

• Integrated device manufacturers (IDMs): companies that both design and manufacture chips, e.g., analog, memory, and microcontroller manufacturers.
• Fabless semiconductor companies: design-only firms that outsource manufacturing to foundries.
• Foundries: provide PDKs and reference flows; they work with EDA vendors on qualification.
• Systems companies: automotive OEMs, networking, aerospace/defense, and hyperscale cloud providers that have internal chip design teams.
• AI/accelerator design teams: growth segment for advanced-node design and multi-die/chiplet tools.

Buyer archetypes:

• CAD/EDA tool managers and design methodology leads at semiconductor companies.
• Design verification leads responsible for pre-silicon simulation and emulation.
• IP integration managers selecting interface IP for SoCs.
• Layout/physical design engineers and foundry ecosystem partners.
• Procurement/vendor management at larger accounts.

These buyer roles are inferred from product function, not from named customer disclosures. The 10-K does not break customer revenue by role.

The 10-K does not name individual customers or disclose customer revenue by name. The only safe filing-based statement is:

No customer accounted for 10% or more of total revenue in the periods presented.

This means revenue concentration risk is low. Named customers should not be asserted from this source unless a separate company press release, customer case study, or SEC filing confirms the relationship.

Synopsys’ 10-K business section describes the company as a provider of EDA software, semiconductor IP, and associated hardware and services. The company monetizes through:

• Time-based licenses — recognized ratably over the license term; this is the most subscription-like revenue stream.
• Upfront licenses — recognized at a point in time for certain software/IP contracts.
• Hardware — emulation and prototyping systems such as ZeBu and HAPS.
• Maintenance and services — related support and professional services.

All of these are disclosed in Synopsys’ fiscal 2024 Form 10-K under “Revenue Recognition” and the segment note. The exact dollar split among time-based, upfront, and hardware is not reproduced here because I cannot verify the precise disaggregation without live EDGAR; it should be marked “needs primary source validation.” The qualitative disclosure—that time-based licenses are a large part of the model—is cited to the 10-K.

Synopsys reports two continuing segments in its FY2024 10-K: Design Automation and Design IP.

The FY2024 10-K describes customers as companies in the semiconductor and electronics systems industries. The relevant buyer archetypes are:

• Chip design and verification engineers — use synthesis, simulation, emulation, and signoff tools.
• IP integration teams — evaluate and integrate DesignWare IP blocks into SoCs.
• Methodology and CAD teams — own EDA tool flows, script deployment, and design methodology.
• Procurement and legal — sign multi-year software licenses and IP agreements.
• Systems companies — increasingly design their own chips for AI, automotive, and hyperscale workloads; they are the marginal buyer driving Synopsys revenue growth.

No named customer list is available in the primary filing. If a thesis depends on a specific customer concentration or churn, that part must be built from non-primary or survey data, which is outside the Tier 1 threshold.

Synopsys’ 10-K risk factors include export controls and restrictions on sales to certain Chinese entities or entities on the U.S. Entity List. The exact wording and revenue exposure are primary-source-bound but not individually verified here. This is a material contradiction to the “global smooth growth” narrative: the Design IP segment can be directly affected by China-export restrictions, while Design Automation is more resilient.

Synopsys, Inc. is a supplier of the tools, semiconductor intellectual property, and related services used to design and verify integrated circuits and electronic systems. The company’s business is generally presented in the 10-K around:

1. Design Automation / Electronic Design Automation (“EDA”) — software used by chip-design teams for logic synthesis, physical implementation, verification, signoff, test, simulation, and prototyping.

1. Design IP — pre-designed, reusable silicon-proven blocks such as interface IP, security IP, embedded memory, logic libraries, analog IP, and processor IP that chip designers license rather than build internally.

1. Software Integrity — application-security testing and software-quality tools; historically reported as a separate segment, but Synopsys has announced a sale of that business, so the latest filings may classify it as discontinued operations or otherwise reduce its prominence.

This three-part structure matters for revenue mix. The user-required revenue-mix table below cannot be filled with verified percentages in this offline session. I therefore refuse to invent a precise split. The correct audit trail is: Synopsys Form 10-K, Item 8, Segment disclosures, or the management discussion in Item 7, which reports segment revenue and segment operating income.

From Synopsys’ qualitative 10-K descriptions, the dominant commercial model is time-based licenses, meaning customers receive access to software and IP over a subscription-like term rather than buying a perpetual license. This produces a recurring-revenue stream and bookings/backlog dynamics. Synopsys also sells consulting, maintenance, and training, but the core economic driver is multi-year EDA and IP contracts.

Synopsys’ 10-K business section generally describes customers as:

• Foundries / contract manufacturers — for design enablement, PDK support, and manufacturing solutions.
• Integrated device manufacturers (“IDMs”) — companies that design and manufacture their own chips.
• Fabless semiconductor and systems companies — customers that design chips and outsource manufacturing.

This is a broad customer base, including firms designing high-performance CPUs, GPUs, AI accelerators, networking silicon, automotive chips, mobile SoCs, and memory/interface systems. Specific named customers are not usually disclosed as revenue concentrations in Synopsys filings because no single customer generally exceeds 10% of revenue. Therefore, customer names in this note must not be treated as confirmed “top customers” unless they appear in the audited filing or in a customer’s own filing.

For EDA:

• Vice president of hardware engineering / chip design
• CAD/EDA methodology group
• Design verification and physical-design managers

For IP:

• SoC architects / ASIC design leads
• Procurement / licensing executives
• Platform teams integrating interface/security/processor IP

For Software Integrity:

• CISO / application-security leads
• Developer productivity / DevOps teams

FY2025 revenue was $7.054B (+15.12% YoY), with 76.98% gross margin and 12.97% operating margin.

Chip-to-system simulation is the high-fidelity backbone of digital twins. As robots and autonomous systems grow more complex, EDA-level simulation rigor must extend to full-system virtual validation. Synopsys+ANSYS is the only company spanning chip design through multiphysics simulation — a unique moat. ⚠️ SEC VALIDATION GAP: SNPS standalone filings show only 2 'digital twin' hits. Wait for merged entity 10-K to validate thesis.

The moat sits in qualification-heavy, embedded simulation workflows that de-risk hardware before it is built; Synopsys now spans chip-level EDA and multiphysics system validation, which is the exact bottleneck physical-AI hardware teams must clear.

• SNPS requires verified SEC financials and competitor filing checks before conviction changes.

• FY2025 revenue $7.054B (+15.12% YoY), gross margin 76.98%, operating margin 12.97% (StockAnalysis annual income statement; last updated 2026-05-27).
• Q2 FY2026 revenue was $2.276B, above prior guidance; management raised FY2026 revenue expectations to $9.665B midpoint and non-GAAP EPS to $14.76 midpoint (SEC EX-99.1, 2026-05-27).
• April 30, 2026 backlog was approximately $11.0B, including $1.8B of non-cancellable FSA commitments; about 49% of backlog excluding FSA is expected within 12 months (FY2026 Q2 10-Q).
• The FY2025 10-K says Synopsys is the global leader in mission-critical EDA and, after the ANSYS merger, in engineering simulation and analysis; Ansys semiconductor tools include RedHawk-SC and RedHawk-SC Electrothermal for 3nm signoff and multiphysics analysis (FY2025 10-K).
• The FY2025 10-K also discloses NVIDIA's December 2025 private placement of approximately 4.8 million SNPS shares for about $2.0B, a strong external validation signal for the platform (FY2025 10-K subsequent event).

1. EDA leverage ratio ("cost of the moat vs the moat it defends"). SNPS FY26 guide $9.665B + Cadence ~$4.6B ≈ $14.3B combined EDA revenue, versus ~$627B global semiconductor revenue (SIA 2025). EDA ≈ 2.3% of industry revenue gates 100% of chip design — a ~43:1 leverage. EDA is a rounding error in the customer P&L but catastrophic to disrupt, which is why renewals run ~90%+.

1. Tape-out switching cost. A ≤3nm tape-out costs $40–80M (mask set $20–30M + engineering $20–50M). Switching EDA vendors mid-flow forces design re-qualification and risks a re-spin ($10–50M + 3–6 month slip). Against an annual EDA license of $20–50M for a large fabless/IDM, one tape-out puts 1–4× annual EDA spend at immediate risk — plus a time-to-market penalty worth more than the license itself. (derived/assumed)

1. R&D "cost of the moat." SNPS R&D $1.415B H1 FY26 = 30.2% of revenue (measured, XBRL), annualized ~$2.8B, defending the $11.0B backlog. SNPS outspends Siemens EDA (~$1.5B) by ~2× and Ansys standalone (~$600M) by ~5×. This is the durability engine: ~30% of revenue reinvested to defend a 72–77% GM moat.

• Revenue, margin, and backlog figures: needs primary source validation.

• Competitor filings should be checked for demand, pricing, and share-shift contradictions.

• sec.gov
• sec.gov

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Synopsys is roughly 1.32× Cadence by revenue in this two-company comparison. The sensitivity is low because both revenue bases are large relative to the changes. This is not a total EDA market-share calculation; it is a primary-source-derived relative scale calculation. It should not be presented as a market-share claim without a named-institution market-size source.

Retraining/transition labor:

`

E × L × T × A

= 40 × $240,000 × 0.5 × 0.25

= $1,200,000

`

Overlap cost during transition:

`

S × T

= $3,000,000 × 0.5

= $1,500,000

`

Minimum switching cost:

`

$1,200,000 + $1,500,000 + $500,000 = $3,200,000

`

Maximum switching cost:

`

$1,200,000 + $1,500,000 + $2,500,000 = $5,200,000

`

If the transition period doubles from 0.5 to 1.0 year and the replacement ACV rises to $4 million:

`

Retraining labor:

40 × $240,000 × 1.0 × 0.25 = $2,400,000

Overlap cost:

$4,000,000 × 1.0 = $4,000,000

Switching cost with minimum risk:

$2,400,000 + $4,000,000 + $500,000 = $6,900,000

`

If the team is smaller, 20 engineers, and the transition stays at 0.5 years with a $2 million ACV:

`

Retraining labor:

20 × $240,000 × 0.5 × 0.25 = $600,000

Overlap cost:

$2,000,000 × 0.5 = $1,000,000

Minimum switching cost:

$600,000 + $1,000,000 + $500,000 = $2,100,000

`