PowerLattice
Component
Vancouver, WA startup putting voltage regulation inside the processor package with a power-delivery chiplet.
PowerLattice builds a power-delivery chiplet that moves voltage regulation off the PCB and into the processor package, placing it a few hundred micrometres from the accelerator die instead of inches away. The part monolithically combines miniaturised proprietary on-die magnetic inductors, voltage-control circuitry and a programmable control layer on one silicon die, at roughly 5 A/mm2 current density and a z-height thin enough to mount at the substrate land side or embed in the substrate or interposer. Multiple chiplets parallel up to build the full power topology for a given SoC, so a customer can shape power domains to their package. The claim is more than 50% lower total compute power, effectively doubling performance per rack. It is pre-revenue: engineering samples target 1 kW-plus processors.
Research mapping
Physical AI / Grid, Power & Thermal Infrastructure (L2) / Component
Evidence boundary
Original analysis and independent corroboration remain under development. Commercial scale and durable technical advantage remain under review.
What makes it defensible
On-die integrated magnetics: shrinking the inductor into the package is the step two decades of power-delivery attempts could not commercialise, and it is what makes in-package regulation viable at 2,000 W per chip.
Position in the stack: Component bottleneck (pa-2) inside the accelerator package: it sells silicon to the SoC and accelerator makers who must hit power ceilings, and the position is defensible because the magnetics process and control loop sit between the foundry and the system designer.
Who buys it
Founding team
Dr. Peng Zou — Co-founder, CEO & President — Engineering leadership in power management and integrated magnetics at Qualcomm, NUVIA and Intel, with issued and pending patents in the space.
Gang Ren — Co-founder & Head of Engineering — Analog IC and power-management engineering veteran from Qualcomm, NUVIA and Intel.
Sujith Dermal — Co-founder & Head of Systems & Apps — System design and applications engineering leader across Qualcomm, NUVIA and Intel.
SourceFinancing detail
- Last round
- Series A ($25M, Nov 2025)
Investors: Playground Global, Celesta Capital
Mapped funds and investors
Direct relationships supported by published evidence.
Reported holdings as-of
No sourced relationships mapped yet.
Disclosed investment history
| Fund / investor | Last sourced | Relationship | Evidence |
|---|---|---|---|
| Playground Global | lead | Source |
Showing up to four relationships in each group. ETF weights describe the fund’s portfolio, not ownership of this company. Private investment history does not establish current ownership.