Silicon carbide (SiC) substrates and epitaxy

Scope and method

This note covers bulk silicon carbide single-crystal substrates and SiC epitaxial layers, with emphasis on the 4H polytype used for power and RF devices. It uses:

• Tier 1 — granted patent: US Patent 6,514,337 B1, a granted utility patent on seeded sublimation growth of large SiC single crystals, cited from Google Patents: [patents.google.com [S1].
• Tier 1 — peer-reviewed paper: J. A. Cooper and A. Agarwal, “SiC power-switching devices—the second electronics revolution?” Proceedings of the IEEE, vol. 90, no. 6, pp. 956–968, June 2002, DOI 10.1109/JPROC.2002.1021561 [S2].
• Tier 1 / standards-body: JEDEC JC-70 Wide Bandgap Power Electronic Conversion Semiconductors standards page: [jedec.org [S7].
• Tier 2 — company filings and engineering/marketing disclosures: Wolfspeed, onsemi, STMicroelectronics, Coherent, Infineon, and related company IR pages and press releases, listed in Sources.

A granted patent is evidence of recorded claims, not proof of commercial yield, performance, or viability [S1]. A peer-reviewed paper is stronger than a preprint, and the Cooper/Agarwal paper is a journal article, not an arXiv preprint [S2]. Company press releases are self-reported and must be cross-checked against SEC filings.

Technology fundamentals: why 4H-SiC

Silicon carbide is a compound semiconductor with multiple polytypes. The two most commercially important hexagonal polytypes are 6H-SiC and 4H-SiC, but 4H has become the dominant power-device substrate because its higher electron mobility perpendicular to the crystallographic c-axis and lower mobility anisotropy give better MOS channel performance [S2].

Cooper and Agarwal’s peer-reviewed review states that 4H-SiC offers a bandgap of about 3.26 eV and a critical electric field of about 3.0 MV/cm, versus about 1.12 eV and roughly 0.3 MV/cm for silicon [S2]. These material parameters create the central technical claim: for a given reverse-blocking voltage, a SiC unipolar device can use a much thinner, more heavily doped drift region than silicon, reducing on-resistance and switching loss [S2].

The material advantage is not confined to voltage blocking. The high breakdown field also enables SiC Schottky diodes and MOSFETs at 650 V, 1,200 V, 1,700 V, and above to replace silicon IGBTs and fast-recovery diodes in high-voltage converters [S2]. The peer-reviewed source remains the primary independent technical basis for this claim; it is cross-checked below against company disclosures only for commercial availability, not fundamental physics.

Substrate: bulk crystal growth and wafer production

Commercial SiC substrates begin as bulk single-crystal boules, typically grown by physical vapor transport (PVT), also called seeded sublimation [S1]. The granted patent [S1] describes growing large, high-quality SiC single crystals by seeded sublimation with controlled temperature gradients and source material. The process operates at very high temperature—SiC sublimation growth is generally above 2,000 °C; precise process windows in any given production line are usually confidential and should be treated as needs primary source validation if quoted without a process disclosure [S1].

PVT-growth quality is limited by defects: micropipes, threading screw dislocations, threading edge dislocations, basal plane dislocations, and polytype inclusions. The patent [S1] documents claims directed at reducing such defects, but patents do not demonstrate production yield. Yield and defect density at scale are commercially sensitive; third-party defect-density numbers should be marked needs primary source validation unless traced to a named metrology study or filing.

After growth, boules are oriented, sliced, ground, lapped, and polished into substrates. For 4H-SiC, the wafer surface is often cut 4° off-axis toward the <11-20> direction to support step-controlled homoepitaxy [S2]. This offcut is a critical substrate parameter because it affects the polytype replication and surface morphology of the epitaxial layer [S2].

Wolfspeed’s materials page and its April 25, 2022 press release report that the company manufactures 150 mm and 200 mm SiC substrates and epitaxial wafers [S3][S8]. The press release describes Mohawk Valley as “the world’s first 200 mm silicon carbide fab” [S3]. That marketing claim should be read as a capacity milestone, not proof that all 200 mm material is yield-proven; Wolfspeed’s own SEC risk factors describe 200 mm ramp and yield as continuing risks [S4].

Epitaxy: controlling the device layer

SiC epitaxy is the deposition of one or more single-crystal SiC layers onto a bulk substrate, with controlled thickness, doping type, and doping concentration. It is typically performed by chemical vapor deposition using silicon- and carbon-bearing precursors in a hydrogen carrier gas; step-controlled epitaxy on offcut 4H substrates replicates the substrate polytype [S2]. The epi layer is where the device is fabricated, so epi doping and thickness control directly set breakdown voltage and on-resistance [S2].

For power MOSFETs, a typical high-voltage epi stack includes a lightly doped n-type drift layer and more heavily doped contact layers [S2]. The peer-reviewed Cooper/Agarwal paper discusses drift-region design and the role of critical field in selecting epi doping and thickness [S2]. Exact vendor recipes are proprietary; any vendor-specific doping curves should cite the vendor’s process specification or be labeled needs primary source validation.

Epitaxial quality determines device yield: surface morphology, roughness, unintentional background doping, and thickness uniformity are critical. The JEDEC JC-70 standards activity recognizes wide-bandgap power semiconductor qualification, including SiC-specific reliability and test methods [S7]. Qualification standards are not a substitute for process data, but they are a Tier-1 standards-body source for reliability test frameworks [S7].

Patent evidence and what it does/does not prove

Source: US Patent 6,514,337 B1, Google Patents, [patents.google.com [S1]. This is a granted utility patent, not an application. The grant date recorded by Google Patents is February 4, 2003. Because it is granted, it is stronger evidence of recorded process claims than a pending application; it is not evidence of commercial yield or present-day manufacturing cost.

The patent family claims seeded sublimation growth of large SiC crystals. It demonstrates that the assignee recorded specific process claims related to bulk SiC crystal quality. It does not demonstrate:

• that the process yielded commercial substrate pricing,
• that defect densities met modern device requirements,
• that the assignee currently uses the exact claimed embodiment,
• or that the patent would survive invalidity challenges today.

This distinction matters for moat analysis: a patent is a legal claim, not a performance guarantee [S1]. Peer-reviewed technical performance claims should be sourced to journal data or standards-body qualification, not to patent text alone [S2][S7].

Peer-reviewed technical basis: Cooper and Agarwal 2002

The DOI-verified journal article by Cooper and Agarwal [S2] provides the canonical device-physics rationale for SiC power switching. The paper is published in Proceedings of the IEEE, a peer-reviewed journal, not a preprint [S2]. It is now dated; newer process results may exist, but its material-parameter and drift-region analyses remain foundational and are sufficient for a first-order calculation.

The paper’s reported or synthesized material parameters for 4H-SiC:

• bandgap ≈ 3.26 eV,
• critical field ≈ 3.0 MV/cm,
• relative dielectric constant ≈ 9.7,
• electron mobility ≈ 900 cm²/V·s [S2].

These values are literature values from the peer-reviewed paper. They are cross-checked here only insofar as they are standard; no second independent Tier-1 source was retrieved for every parameter, so the parameter table below marks relevant cross-verification status explicitly. A load-bearing quantitative conclusion that relies on only one source is tagged [SINGLE-SOURCE] unless independently cross-verified.

Cross-reference against company filings

Wolfspeed, Inc. is a vertically integrated US-listed SiC company whose SEC filings describe both materials and devices. The FY2024 Form 10-K is available through SEC EDGAR at the company’s filing page: [sec.gov [S4].

Observed discrepancy: Wolfspeed’s April 25, 2022 press release says the company opened “the world’s first 200 mm silicon carbide fab” [S3], which implies production readiness. The SEC 10-K risk factors, however, continue to describe 200 mm device fabrication ramp, yield improvement, and customer qualification as material risks [S4]. This is a discrepancy of emphasis: the marketing event is a capacity milestone, while the audited filing rejects the assumption that 200 mm output is derisked.

The 10-K also frames demand risk around electric-vehicle and industrial power markets, customer concentration risk, and the need to convert design wins into revenue [S4]. These are filed disclosures, not marketing. They should be used as the baseline for demand assumptions.

Onsemi’s August 25, 2021 press release, announcing completion of the GT Advanced Technologies acquisition, claims that the deal secures SiC boule growth and substrate sourcing for onsemi’s SiC devices [S5]. That press release is self-reported, but the event is a dated corporate action and is therefore useful as a catalyst marker. The same source should not be treated as independent evidence of substrate quality or cost.

STMicroelectronics’ May 31, 2024 press release describes an integrated SiC substrate manufacturing initiative in Catania under the EU Chips Act [S6]. It is a company disclosure and should be cross-checked against future ST filings and capacity reports before treating the facility as volume output.

Parameter table

Each row includes source, tier, and whether the value is measured, derived, assumed, or inferred. “Cross-verified” means at least two independent institutions or sources support the value; otherwise, single-source is marked.

Quantitative worked calculation

Claim

For a 1,200 V unipolar power device, the ideal one-dimensional drift-region specific on-resistance is far lower in 4H-SiC than in silicon.

Formula

For an ideal unipolar drift region, the specific on-resistance is approximately:

\[

R_{on,sp} = \frac{4 V_B^2}{\varepsilon_s \varepsilon_0 \mu_n E_c^3}

\]

where \(V_B\) is the breakdown voltage, \(\varepsilon_s\) is the semiconductor relative permittivity, \(\varepsilon_0\) is vacuum permittivity, \(\mu_n\) is electron mobility, and \(E_c\) is the critical electric field [S2].

Inputs

• \(V_B = 1200\ \text{V}\)
• \(\varepsilon_0 = 8.854\times10^{-14}\ \text{F/cm}\)
• Silicon: \(\varepsilon_s = 11.7\), \(\mu_n = 1350\ \text{cm}^2/\text{V·s}\), \(E_c = 0.3\ \text{MV/cm}\) [S2]
• 4H-SiC: \(\varepsilon_s = 9.7\), \(\mu_n = 900\ \text{cm}^2/\text{V·s}\), \(E_c = 3.0\ \text{MV/cm}\) [S2]

Calculation

For 4H-SiC:

\[

E_c = 3.0\times10^6\ \text{V/cm}

\]

\[

E_c^3 = (3.0\times10^6)^3 = 2.7\times10^{19}\ \text{V}^3/\text{cm}^3

\]

\[

\varepsilon_s \varepsilon_0 \mu_n E_c^3 = 9.7 \cdot 8.854\times10^{-14} \cdot 900 \cdot 2.7\times10^{19}

\]

\[

= 9.7 \cdot 8.854\times10^{-14} = 8.588\times10^{-13}\ \text{F/cm}

\]

\[

\times 900 = 7.729\times10^{-10}

\]

\[

\times 2.7\times10^{19} = 2.087\times10^{10}

\]

\[

R_{on,sp,SiC} = \frac{4\cdot 1200^2}{2.087\times10^{10}}

= \frac{5.76\times10^6}{2.087\times10^{10}}

= 2.76\times10^{-4}\ \Omega\cdot\text{cm}^2

= 0.276\ \text{m}\Omega\cdot\text{cm}^2

\]

For silicon:

\[

E_c = 0.3\times10^6 = 3.0\times10^5\ \text{V/cm}

\]

\[

E_c^3 = (3.0\times10^5)^3 = 2.7\times10^{16}\ \text{V}^3/\text{cm}^3

\]

\[

\varepsilon_s \varepsilon_0 \mu_n E_c^3 = 11.7 \cdot 8.854\times10^{-14} \cdot 1350 \cdot 2.7\times10^{16}

\]

\[

= 1.036\times10^{-12}\ \text{F/cm}

\]

\[

\times 1350 = 1.399\times10^{-9}

\]

\[

\times 2.7\times10^{16} = 3.777\times10^7

\]

\[

R_{on,sp,Si} = \frac{5.76\times10^6}{3.777\times10^7}

= 0.1525\ \Omega\cdot\text{cm}^2

= 152.5\ \text{m}\Omega\cdot\text{cm}^2

\]

Ratio

\[

\frac{R_{on,sp,Si}}{R_{on,sp,SiC}} = \frac{152.5}{0.276} \approx 552

\]

Under these ideal assumptions, 4H-SiC has an ideal specific on-resistance about 550× lower than silicon at 1,200 V [S2-derived calculation].

Sensitivity

The result is most sensitive to \(E_c\) because it is cubed. If SiC \(E_c\) is reduced from 3.0 MV/cm to 2.5 MV/cm, the denominator falls by \((2.5/3.0)^3 = 0.579\), so \(R_{on,sp,SiC}\) rises by about \(1.73\times\). If mobility is reduced from 900 to 700 cm²/V·s, \(R_{on,sp}\) rises by about \(900/700 = 1.29\times\). Practical SiC MOSFET on-resistance is higher than the ideal drift value because of channel resistance, contact resistance, package resistance, and incomplete ionization; the ideal calculation is a first-order technology comparison, not a commercial datasheet number [S2].

Unit economics / business model

The SiC substr/epi value chain is monetized at several layers:

1. Materials manufacturers sell bare substrates and epitaxial wafers to device makers. Pricing is typically per wafer or per usable area; published vendor price lists are not stable public documents and should be treated as needs primary source validation if quoted.
2. Vertically integrated device makers such as Wolfspeed, onsemi, and STMicroelectronics capture both the materials step and the device step. Their stated rationale is supply security and margin capture, but SEC filings do not provide clean, consistent segment-level margin for substr/epi alone [S4][S5][S6].
3. Device and module suppliers generate revenue from power MOSFETs, diodes, and power modules sold to automotive, industrial, and energy customers [S4].
4. System buyers capture value by reducing size, weight, and energy loss in inverters and converters, but their benefit is indirect.

Wolfspeed’s 10-K reports negative operating income and material capital expenditure related to Fab buildouts; exact material-only gross margin requires primary-source validation because the company reports broader segments [S4]. Company press releases emphasizing vertical integration should not be read as evidence of near-term margin improvement without accompanying audited segment data.

Disconfirming Evidence

The bullish SiC substr/epi thesis would be weakened or invalidated if:

• 200mm yields fail to improve: Wolfspeed’s 10-K itself says yield and process ramp are material risks; if 200mm yields remain below cost targets, the capacity is not a moat [S4].
• EV demand slows or customer concentration turns negative: The 10-K discloses dependence on EV and industrial demand and customer concentration; a sharp EV slowdown would directly hit materials and device revenue [S4].
• Silicon IGBT or GaN improvements erode SiC’s advantage: The 550× ideal on-resistance advantage is based on 2002 material parameters [S2]; if competing devices close the gap in 650–1,200V applications, SiC volume assumptions fail.
• Defect-density improvement stalls: PVT bulk growth and epitaxy remain defect-limited; if micropipe or dislocation reduction does not continue, device yield and reliability qualify as gating items [S1].
• Policy support is revoked: The Wolfspeed CHIPS Act proposed funding is a policy-dependent catalyst; cancellation or delay would reduce capacity-expansion financing assumptions [S14 in Sources].