Gallium nitride (GaN) power semiconductors on silicon

Executive summary

Gallium nitride (GaN) power semiconductors on silicon are lateral AlGaN/GaN high-electron-mobility transistors (HEMTs) fabricated on low-cost silicon wafers. The silicon substrate gives the technology access to mature 150 mm and 200 mm CMOS-style fab infrastructure, while the GaN/AlGaN heterostructure provides a two-dimensional electron gas (2DEG) with high carrier density and mobility. Commercially, GaN-on-Si is concentrated in 650 V and emerging 900 V power-conversion applications: fast chargers, data-center power supplies, adapters, solar microinverters, and automotive on-board chargers/DC-DC converters [S1][S2][S5][S7].

The core technical trade-off is that GaN-on-Si is predominantly a lateral device technology. A conductive silicon substrate and stress-management buffer layers make true vertical high-voltage GaN devices on silicon difficult. That is why GaN-on-Si competes most directly with silicon super-junction MOSFETs at 650 V, while silicon carbide (SiC) remains preferred for many >1.2 kV high-power traction applications [S1][S2].

Technical foundation

1.1 Device physics and structure

GaN has a bandgap of about 3.4 eV, roughly three times that of silicon, and a critical electric field of about 3.3 MV/cm, which is an order of magnitude above silicon’s typical critical field. In an AlGaN/GaN heterojunction, spontaneous and piezoelectric polarization produce a 2DEG at the AlGaN/GaN interface with sheet carrier density on the order of 1×10^13 cm^-2 and electron mobility of about 1,500–2,000 cm²/V·s [S1][S2].

Because conventional AlGaN/GaN HEMTs are normally-on depletion-mode devices, power-switch products must implement a normally-off architecture. The main commercial approaches are:

• p-GaN gate HEMTs: a p-type GaN layer under the gate raises band energy and depletes the channel at zero gate bias.
• Cascode/direct-drive configurations: a low-voltage silicon MOSFET in series with a depletion-mode GaN HEMT to create normally-off behavior.
• MIS/MOS-gated HEMTs: insulated-gate structures to reduce gate leakage and widen gate voltage swing.

The choice of normally-off architecture affects gate reliability, driving simplicity, and dynamic on-resistance behavior. This is one reason patents, rather than a single product datasheet, dominate early moat analysis [S2][S3].

IP caveat: US Patent 8,350,294 B2, granted on 2013-01-08 and assigned to Efficient Power Conversion LLC, records claims for an enhancement-mode GaN HEMT. It is Tier 1 evidence of a recorded legal claim, not proof that the claimed device meets production yield, reliability, or cost targets. A granted patent does not independently demonstrate commercial viability or performance [S3].

1.2 Why silicon substrates?

GaN-on-Si leverages silicon wafer cost, large wafer diameters, and existing CMOS fab infrastructure. But GaN and silicon have large lattice and thermal-expansion mismatch. Managing that mismatch requires multi-layer buffer structures—typically AlN nucleation layers followed by transition AlGaN layers and strain-engineering layers. Poor buffer quality creates traps that are a root cause of dynamic on-resistance and current-collapse degradation [S1][S2].

The 2018 GaN power electronics roadmap states that 150 mm and 200 mm silicon substrates were then the production mainstream, with 300 mm development underway [S1]. Infineon’s 300 mm GaN pilot line announcement is a later commercial milestone confirming the direction toward 300 mm GaN-on-Si manufacturing [S10].

1.3 Reliability and dynamic RDS(on)

Unlike silicon MOSFETs, GaN power switches exhibit dynamic on-resistance: after off-state voltage stress, trap capture in the buffer, surface, or epitaxial layers can temporarily raise RDS(on). The magnitude is stress-voltage-, frequency-, and temperature-dependent, and it must be characterized per application. This is a recognized commercial risk and a central focus of reliability standards work [S2][S4].

JEDEC’s JC-70 committee addresses wide-bandgap power electronic conversion semiconductors, including GaN. Standards-body activity does not itself guarantee product reliability, but it provides a documented framework for qualifying dynamic RDS(on), switching safe operating area, and lifetime behavior [S4].

Quantitative worked calculation: Baliga figure-of-merit for specific on-resistance

To make the “GaN has a smaller die for the same on-resistance” claim concrete, we can estimate the theoretical specific on-resistance of a unipolar GaN power device using the Baliga figure-of-merit. The common expression is:

\[

R_{sp} = \frac{4 V_B^2}{\varepsilon_s \mu_n E_c^3}

\]

where:

• \(R_{sp}\) = specific on-resistance, Ω·cm²
• \(V_B\) = blocking voltage, V
• \(\varepsilon_s\) = semiconductor permittivity, F/cm
• \(\mu_n\) = electron mobility, cm²/V·s
• \(E_c\) = critical electric field, V/cm

Material inputs used here are taken from the GaN parameters reported in the Amano roadmap and Chen review: GaN \(\varepsilon_r \approx 9.5\), \(\mu_n \approx 1{,}500\) cm²/V·s, \(E_c \approx 3.3\) MV/cm. Silicon comparison uses common silicon values \(\varepsilon_r \approx 11.7\), \(\mu_n \approx 1{,}350\) cm²/V·s, \(E_c \approx 0.3\) MV/cm [S1][S2].

For \(V_B = 650\) V:

GaN:

\[

\varepsilon_s = 9.5 \times 8.854 \times 10^{-14} \approx 8.41 \times 10^{-13}\ \text{F/cm}

\]

\[

R_{sp,\text{GaN}} = \frac{4 \times 650^2}

{8.41 \times 10^{-13} \times 1{,}500 \times (3.3 \times 10^6)^3}

\]

Denominator:

\[

8.41 \times 10^{-13} \times 1{,}500 = 1.2615 \times 10^{-9}

\]

\[

(3.3 \times 10^6)^3 = 3.5937 \times 10^{19}

\]

\[

1.2615 \times 10^{-9} \times 3.5937 \times 10^{19} = 4.53 \times 10^{10}

\]

\[

R_{sp,\text{GaN}} = \frac{1.69 \times 10^6}{4.53 \times 10^{10}}

\approx 3.73 \times 10^{-5}\ \Omega\text{·cm}^2

\quad (\approx 0.037\ \text{m}\Omega\text{·cm}^2)

\]

Silicon:

\[

\varepsilon_s = 11.7 \times 8.854 \times 10^{-14} \approx 1.036 \times 10^{-12}\ \text{F/cm}

\]

\[

R_{sp,\text{Si}} = \frac{1.69 \times 10^6}

{1.036 \times 10^{-12} \times 1{,}350 \times (0.3 \times 10^6)^3}

\]

Denominator:

\[

1.036 \times 10^{-12} \times 1{,}350 = 1.399 \times 10^{-9}

\]

\[

(0.3 \times 10^6)^3 = 2.7 \times 10^{16}

\]

\[

1.399 \times 10^{-9} \times 2.7 \times 10^{16} = 3.78 \times 10^7

\]

\[

R_{sp,\text{Si}} = \frac{1.69 \times 10^6}{3.78 \times 10^7}

\approx 0.045\ \Omega\text{·cm}^2

\]

Result: the theoretical specific on-resistance advantage at 650 V is:

\[

\frac{R_{sp,\text{Si}}}{R_{sp,\text{GaN}}} \approx \frac{0.045}{3.73 \times 10^{-5}} \approx 1{,}200

\]

Interpretation and sensitivity

This is a theoretical material-limit calculation, not a datasheet comparison. Real GaN HEMTs include access resistance, contact resistance, gate/drain spacing for breakdown margin, and buffer/substrate losses, so production devices operate well above the Baliga limit. The calculation is most sensitive to \(E_c\) because it appears cubed: a ±10% change in \(E_c\) changes \(R_{sp}\) by roughly −25%/+33%. A ±10% mobility error changes \(R_{sp}\) linearly by only about ±10%. Published 650 V GaN-on-Si HEMTs generally achieve specific on-resistance in the low-single-digit mΩ·cm² range, still well below silicon at the same voltage class [S1][S2].

Parameter table

Where a cell says “company self-report,” the number is offered by a commercial vendor and is not an independent Tier 1 measurement.

Manufacturing and supply chain

GaN-on-Si power devices are made with MOCVD epitaxy on silicon substrates, followed by standard front-end wafer processing, thin-film deposition, etch, metallization, and often wafer-level packaging. The silicon substrate enables large-wafer processing and compatibility with conventional wafer fabs, but the epi and buffer layers are not standard silicon processes. Control of the buffer quality is central to yield and reliability [S1][S2].

Companies monetize this technology through several supply-chain positions:

• Fabless GaN IC design: Navitas Semiconductor sells GaN power ICs that integrate gate driver, protection, and power FET into one die. Its business model depends on third-party foundries [S5][S9].
• Integrated device manufacturer (IDM) model: Infineon, Texas Instruments, STMicroelectronics, and Power Integrations sell GaN FETs, GaN power stages, or GaN-based switcher ICs through their own product lines [S6][S7][S8][S11].
• Epitaxy and MOCVD equipment: Veeco and Aixtron-style deposition tools are needed to grow the AlGaN/GaN layers. Veeco’s public product literature documents GaN MOCVD systems [S14].
• Patent/IP layer: granted patents, including S3, are asserted to protect normally-off gate architectures and process steps [S3].

Foundry and risk concentration: Navitas’s SEC EDGAR filing index shows that the company files 10-K disclosures, where it describes risks including reliance on third-party foundries and competition from silicon and SiC power semiconductors. The exact risk-factor wording and any updated customer-concentration figures should be read from the latest 10-K filing linked from SEC EDGAR; exact financial figures are not reproduced here because the specific filing text was not pulled for this note and would be needs primary source validation if quoted [S9].

Adoption and demand context

Company engineering and product pages identify the primary application pull:

• Fast charging and adapters: Navitas and Power Integrations both market GaN for smaller, higher-power USB-PD adapters and chargers. This is the highest-volume consumer entry point for GaN-on-Si [S5][S6].
• Data-center and AI server power: Navitas’s investor materials emphasize GaN in AI data-center power supplies and server power-conversion stages. This claim is company self-report and should be read against SEC risk-factor disclosures [S5][S9].
• Automotive on-board chargers and DC-DC converters: Infineon’s GaN product line targets automotive power conversion, although the highest-power traction inverter segment remains more SiC-oriented [S7][S1].
• Solar and energy storage: Power Integrations and Infineon product documentation includes GaN for solar microinverters and low-to-medium-power converters [S6][S7].

Buyer classes are documented from vendor application pages, not from SEO content or anonymous benchmarks:

• Consumer electronics accessory and charger OEMs/ODMs
• Server and data-center power-supply manufacturers
• Automotive Tier 1 subsystem suppliers
• Solar microinverter and energy-storage converter makers
• Telecom and SMPS power-conversion manufacturers

Contradictions and source cross-checks

6.1 Marketing emphasis vs. filed risk disclosures

Navitas’s investor-relations page positions GaN as a fast-growing replacement for silicon in fast charging, data centers, and EV applications [S5]. Its SEC EDGAR 10-K index points to filings that contain risk factors about competition from silicon and silicon carbide, reliance on third-party manufacturing, and execution risk [S9]. These are not direct factual contradictions in the sense of falsified performance numbers, but they are a discrepancy in emphasis: the marketing materials are adoption-forward, while filed risk disclosures are competition- and execution-forward.

6.2 GaN-on-Si vs. SiC position

GaN-on-Si has demonstrated excellent high-frequency, 650 V-class performance. The Amano roadmap explicitly treats GaN and SiC as complementary wide-bandgap technologies rather than complete substitutes: GaN is strongest in lateral 600–900 V high-frequency applications, while SiC is strongest in vertical 1.2 kV+ high-power applications [S1]. This qualifies marketing language that may imply GaN-on-Si will replace all silicon or all SiC devices.

6.3 Dynamic RDS(on) and “drop-in” claims

Peer-reviewed literature documents dynamic RDS(on) and current collapse as real reliability limitations for GaN power HEMTs [S2]. Product pages may describe “drop-in” or “high reliability” behavior in application-specific contexts, but those are self-reported Tier 2 claims. The JEDEC JC-70 standards activity is better evidence that the industry is still formalizing reliability test methods [S4].

Unit economics / business model

Monetization model: GaN-on-Si power semiconductors are monetized primarily through chip and module sales, not subscriptions or royalties. A fabless supplier such as Navitas sells GaN power ICs to system makers; IDMs such as Infineon, TI, and ST sell standalone GaN FETs, gate-driver co-packaged products, and GaN-based converter ICs [S5][S7][S8].

Margin structure: Exact gross margins vary by company and are not reproduced here because public-statement precision is required; exact Navitas, Power Integrations, TI, or Infineon margin figures should be read from their latest 10-K/20-F filings or quarterly results and would be needs primary source validation if quoted from this note. Fabless GaN suppliers typically carry lower fixed-asset intensity than IDMs because they use foundries, but they also absorb foundry pricing and capacity risk [S9][S5].

Who captures value:

• Fabless GaN design houses capture value through integrated GaN power ICs—typically the highest design differentiation.
• IDMs capture value by selling GaN FETs and integrated converters into existing customer channels.
• Foundries and epitaxy houses capture value through manufacturing volume.
• System OEMs capture value through smaller magnetics, higher switching frequency, and reduced thermal/packaging burden, but only if system-level cost and reliability are validated in production [S1][S2][S5].

Disconfirming Evidence

The bullish GaN-on-Si thesis would be weakened or falsified if the following were observed:

1. Dynamic RDS(on) is not controlled in field use — if independent reliability data show large, repeatable on-resistance increases under normal 650 V converter stress cycles, the efficiency and thermal advantages would erode [S2][S4].
2. SiC costs fall faster than GaN-on-Si costs — if 1.2 kV SiC devices become price-competitive at 650 V or below, GaN-on-Si’s addressable market would compress [S1].
3. 300 mm GaN-on-Si never reaches yield — the cost advantage depends on larger-wafer manufacturing. If 300 mm pilot lines fail to mature, the silicon-substrate cost story weakens [S10].
4. Vertical GaN-on-Si remains unavailable at 1.2 kV+ — if GaN-on-Si cannot move from lateral 650 V into high-power vertical devices, the high-voltage traction market remains SiC-dominated [S1].
5. Foundry capacity or intellectual-property disputes block fabless scaling — if Navitas or similar fabless companies lose foundry access or patent claims are invalidated, unit growth would be constrained [S3][S9].
6. Customer BOM studies show no system-level advantage — if high-frequency magnetics and thermal savings do not offset higher GaN device unit price, adoption slows [S5][S7].

Recent developments

• 2026-10-12 — Navitas ships 24 kW 800 V→12 V GaN DC-DC board built with NVIDIA. Navitas Semiconductor (NVTS) announced a 24 kW, 800 V-to-12 V DC-DC power delivery board (PDB) powered by GaNFast, developed in collaboration with NVIDIA to support the NVIDIA MGX ecosystem and 800 VDC rack architectures for AI data centers; the board is planned to be shown on NVIDIA's AI Factory MGX Wall partner display at OCP Global Summit 2026. Source: Navitas press release, navitassemi.com (company self-reported, Tier 2 — not independently verified).
• Why it is material: this puts GaN into a first-tier AI-rack reference architecture at the 800 V→12 V stage — the highest-voltage step in the rack, historically SiC territory. It is a design-position shift for GaN-on-Si, not yet disclosed revenue.
• What to watch: conversion of MGX design position into named OEM volume; competitive response from SiC incumbents at the same 800 V→12 V node.