Semiconductor thermal processing (diffusion, RTP, SiC annealing)

Executive summary

Thermal processing in semiconductor manufacturing encompasses three related unit operations that this note covers:

1. Diffusion — thermally driven redistribution of dopant atoms into silicon or silicon carbide wafers in batch furnaces.
2. Rapid thermal processing (RTP) — single-wafer, lamp-based heating with high ramp rates, used for ion-implant activation, oxidation, silicide formation, and defect annealing.
3. SiC annealing — high-temperature post-implantation activation and contact annealing for wide-bandgap silicon carbide power devices, typically requiring 1,600–1,900 °C.

The industrial significance is straightforward: every advanced logic, memory, and discrete power device goes through at least one thermal step. SiC annealing is the fastest-growing niche because SiC power devices command higher voltage/temperature operation for electric-vehicle, industrial, and energy infrastructure applications, but SiC implant activation is much harder than silicon implant activation. That difficulty changes the equipment spec: higher temperature, higher uniformity, better surface protection, and often longer process windows.

The strongest moat evidence comes from recorded granted patent claims, not from marketing performance curves. A granted patent is legal evidence of claimed apparatus/method features; it is not proof of commercial yield, thermal uniformity, or customer qualification. The note separates those two evidentiary standards throughout.

Technology physics and process taxonomy

2.1 Diffusion furnaces

Diffusion furnaces are batch systems. Wafers are loaded into a quartz or silicon-carbide tube, heated by external resistive elements, and held at 800–1,150 °C for silicon processes for minutes to hours. The process can be inert, oxidizing, or dopant-bearing. The goal is to drive dopant atoms down a controlled concentration gradient or grow a thermal oxide.

The core physical relationship is the Arrhenius equation for diffusivity:

\[

D(T) = D_0 \exp\left(-\frac{E_a}{k_B T}\right)

\]

Typical silicon dopants such as boron, phosphorus, and arsenic have activation energies on the order of 3–4 eV, which is why furnace thermal budgets are long and temperature control is important. For SiC the activation energies are materially higher, and this is a central reason SiC annealing is a separate problem. Quantitative values for specific SiC dopant \(D_0\) and \(E_a\) are not repeated here because they vary by polytype, impurity species, and defect concentration; the key point from the peer-reviewed SiC literature is that high-temperature anneals are required for usable electrical activation [S3].

2.2 Rapid thermal processing (RTP)

RTP replaces the slow batch furnace with a single-wafer chamber in which high-intensity lamps heat one wafer through the chamber window. The defining characteristics are:

• High ramp rates — often 25–250 °C/s, depending on lamp power and wafer optical properties.
• Short dwell times — seconds to minutes at peak temperature.
• Closed-loop temperature control — pyrometric or thermocouple feedback adjusted through lamp power.

A foundational peer-reviewed treatment of rapid isothermal processing is Singh’s 1988 review in Journal of Applied Physics, which covers the physics, lamp systems, temperature measurement, process uniformity, and applications including annealing, oxidation, and silicide formation [S2]. The review notes that rapid thermal processing gained attention because it enables shorter thermal budgets and better control of dopant redistribution than batch furnaces, but it also introduces wafer-temperature nonuniformity and precise temperature-measurement challenges.

A granted patent from Applied Materials, US 5,155,336 A, describes an RTP apparatus with a lamp array arranged to heat a semiconductor wafer, a susceptor/wafer support, and control structures. Grant number 5,155,336 A, grant date 1992-10-13 [S1]. The patent is Tier 1 evidence of claimed apparatus features, not a measured performance guarantee. It is useful here because it establishes the long-running commercial lineage of lamp-based single-wafer RTP systems, which later vendors iterated for SiC-specific anneal windows.

2.3 SiC annealing

Silicon carbide’s wide bandgap means implanted dopants are difficult to activate. In silicon, a 1,000 °C rapid spike anneal may be adequate for many advanced-node implant activation. In 4H-SiC, implant activation and contact formation generally require 1,600–1,900 °C, depending on dopant species, dose, and polytype. This is discussed in the SiC technology review by Kimoto, published in the peer-reviewed Japanese Journal of Applied Physics, DOI 10.7567/JJAP.54.040103 [S3]. The source is a peer-reviewed review from a leading SiC-device research group.

The high-temperature requirement creates several process integration problems:

• Surface roughening and step bunching on 4H-SiC surfaces at high temperature.
• Silicon out-diffusion from the SiC crystal if temperature is not controlled or if the ambient is not protective.
• Contact metallurgy — ohmic contacts on SiC often require high-temperature anneals, but the metal stack can degrade if the thermal budget is too high.
• Temperature measurement uncertainty at >1,600 °C for pyrometry on semi-transparent or wafers with backside film variations.

For these reasons, SiC annealing is not simply “silicon RTP at higher temperature.” It is a distinct equipment class with protective capping, modified lamp/chamber materials, and process recipes that balance activation against surface degradation [S3].

2.4 Contradictions and trade-offs in the literature

The literature does not present one universally optimal thermal strategy. Key documented contradictions include:

• Furnace vs RTP for SiC activation: Batch furnaces provide good wafer-to-wafer uniformity and long soak times, but the long high-temperature exposure can degrade the SiC surface. Lamp-based RTP can reduce unwanted diffusion and surface degradation, but its temperature range and uniformity at >1,600 °C are more difficult than furnace-based approaches [S2][S3].
• High ramp vs high soak for ohmic contacts: Some contact metallizations require a short high-temperature spike; others need a lower-temperature soak for interfacial reaction. A single RTP recipe cannot satisfy both unless the system supports staged thermal profiles.
• RTP temperature measurement: Singh’s review identifies pyrometer emissivity uncertainty and chamber-window transmission changes as sources of measurement error [S2]. For SiC at 1,700 °C, this problem becomes more severe. The contradiction is that lamp intensity and temperature setpoint are precisely controlled, but wafer emissivity uncertainty can produce large unmeasured temperature errors.

The takeaway: equipment capability claims should be evaluated as upper-bound system specs under optimal wafer conditions, not as guaranteed fab-yield outcomes.

Patent/IP landscape

The granted patent cited here is:

• US 5,155,336 A — “Rapid thermal processing apparatus and method” or closely titled, granted 1992-10-13, assigned in the patent record to a semiconductor-equipment entity associated with Applied Materials. URL: https://patents.google.com/patent/US5155336A/en [S1].

This is a granted utility patent, not an application. It is the stronger class under the note’s source-tier rules. However, it is a process-equipment patent from the early 1990s. It supports the existence of lamp-based single-wafer RTP apparatus claims, but it does not support any specific modern SiC-annealing performance claim.

No patent applications are treated as granted here. If a patent application number appears in secondary sources, it has not been used to support load-bearing technical claims because only granted patents meet the Tier 1 standard for IP evidence.

The distinction matters for moat analysis: a large granted-patent portfolio tells you the recorded invention claims held by a company, not whether those claims map to shipped products or whether the products meet customer yield requirements. Competitors may hold later patents covering SiC-specific anneal processes, chamber materials, or temperature-control schemes that limit freedom-to-operate even if the original RTP patent has expired.

Peer-reviewed literature base

Two Tier 1 peer-reviewed sources anchor the technical discussion:

1. Singh, R. “Rapid isothermal processing,” Journal of Applied Physics, 1988. DOI 10.1063/1.340001 [S2]. This is a review article covering the physics and equipment of rapid thermal processing. It is used here for ramp-rate/thermal-budget context, furnace-vs-RTP trade-offs, and temperature-measurement limitations. The article is older, but it is peer-reviewed and remains a foundational reference for the technique.

1. Kimoto, T. Japanese Journal of Applied Physics, 2015. DOI 10.7567/JJAP.54.040103 [S3]. This is a peer-reviewed SiC technology review covering crystal growth, implantation, activation annealing, oxidation, and device processing. It is used here to support the high-temperature SiC annealing requirement and the process-integration problems introduced by high-temperature exposure.

No arXiv preprint is used as a substitute for journal publication. Every factual claim that depends on these sources is cited to the DOI URL; if a downstream source quotes the paper without the DOI, that downstream source is not used.

Company filings and deployment context

Company filings are Tier 2 for deployment/adoption context and are labeled as self-reported regulatory disclosures. They are not performance proof.

5.1 Applied Materials (AMAT)

Applied Materials is the largest US-headquartered semiconductor-equipment supplier and a major thermal-processing vendor. Its SEC EDGAR listing for 10-K filings is:

https://www.sec.gov/cgi-bin/browse-edgar?action=getcompany&CIK=0000006951&type=10-K&dateb=&owner=include&count=40 [S4]

The 10-K is a regulator-accepted financial and risk disclosure. It discusses semiconductor capital equipment demand, customer concentration, supply-chain constraints, and export-control exposure. Specific thermal-equipment segment financials or RTP uniformities are not repeated here because they require primary-source extraction from the filing text and are not independently verified in this note. A discrepancy risk to watch: company technical marketing may describe single-wafer SiC anneal systems with tight uniformities, but the 10-K generally frames such statements as technical capabilities subject to customer qualification; quantitative marketing numbers do not appear in the same form in the risk-factor section. This is a differences in disclosure context, not necessarily a factual contradiction.

5.2 ASM International N.V. (ASM)

ASM supplies vertical diffusion furnaces, atomic-layer deposition, batch furnace systems, and related thermal equipment. Its SEC EDGAR listing for 20-F/6-K filings is:

https://www.sec.gov/cgi-bin/browse-edgar?action=getcompany&CIK=0000883656&type=20-F&dateb=&owner=include&count=40 [S5]

This source supports the diffusion-furnace supply-chain position. Exact furnace ASPs or gross margins require primary-source extraction from the filing.

5.3 Wolfspeed (WOLF)

Wolfspeed is a vertically integrated SiC substrate, epitaxy, and device producer. It is a buyer of SiC-specific thermal processing and implant-activation equipment. Its SEC EDGAR listing is:

https://www.sec.gov/cgi-bin/browse-edgar?action=getcompany&CIK=0000895419&type=10-K&dateb=&owner=include&count=40 [S6]

The 10-K risk factors include SiC yield, fab ramp, customer qualification, and high-temperature process complexity. This is cited here as evidence that SiC annealing is a production bottleneck for device makers, not a commodity step.

5.4 onsemi (ON)

onsemi manufactures SiC power modules and devices, including trench MOSFETs. It is a buyer of SiC anneal capacity. SEC EDGAR listing:

https://www.sec.gov/cgi-bin/browse-edgar?action=getcompany&CIK=0001094134&type=10-K&dateb=&owner=include&count=40 [S7]

5.5 STMicroelectronics (STM)

STMicroelectronics is a major SiC MOSFET supplier. SEC EDGAR listing:

https://www.sec.gov/cgi-bin/browse-edgar?action=getcompany&CIK=0000932787&type=20-F&dateb=&owner=include&count=40 [S8]

5.6 MKS Instruments (MKSI)

MKS Instruments provides power delivery, temperature measurement, process control, and vacuum/pressure subsystems used in thermal equipment. It is not a chamber OEM but a supplier to thermal-equipment OEMs. SEC EDGAR listing:

https://www.sec.gov/cgi-bin/browse-edgar?action=getcompany&CIK=0001049502&type=10-K&dateb=&owner=include&count=40 [S9]

MKS is included because its temperature/measurement components are exposed to the same SiC anneal process-control problem identified in the physics section.

5.7 Disclosure discrepancy flag

No source in this note quotes a specific published SiC-anneal uniformity number from a company technical document and then confirms that same number in the corresponding 10-K/20-F risk section. Therefore, any specific marketing value for SiC anneal uniformity should be treated as self-reported vendor marketing, not regulatory-confirmed performance. The appropriate tag for such unverified quantitative marketing claims is needs primary source validation.

Parameter table

The parameter table deliberately marks several engineering inputs as assumed or needing primary-source validation rather than inventing precise literature values. Load-bearing performance numbers should be pulled only from peer-reviewed measurement papers or standards-body test methods, not from vendor brochures.

Quantitative worked calculation: RTP lamp-power requirement for a 300 mm silicon wafer

This calculation estimates the absorbed wafer power required to ramp a 300 mm silicon wafer from room temperature to 1,025 °C at different ramp rates. It is a physics-derived estimate, not a vendor-quoted system spec.

Formula:

\[

Q = m c_p \Delta T

\]

\[

P = \frac{Q}{\Delta t} = m c_p r

\]

where:

• \(m\) = wafer mass
• \(c_p\) = specific heat capacity
• \(\Delta T\) = temperature rise
• \(r = \Delta T / \Delta t\) = ramp rate

Inputs:

• Wafer diameter \(d = 30 \text{ cm}\)
• Wafer thickness \(t_w = 0.0775 \text{ cm}\)
• Silicon density \(\rho = 2.33 \text{ g/cm}^3\)
• Specific heat \(c_p = 0.75 \text{ J/g·K}\)
• Temperature rise \(\Delta T = 1000 \text{ K}\)

Mass calculation:

\[

V = \pi \left(\frac{30}{2}\right)^2 \times 0.0775 = \pi \times 225 \times 0.0775 = 54.78 \text{ cm}^3

\]

\[

m = 54.78 \times 2.33 = 127.64 \text{ g}

\]

Energy for 1,000 K rise:

\[

Q = 127.64 \times 0.75 \times 1000 = 95,730 \text{ J}

\]

Power vs ramp rate:

Interpretation and sensitivity:

• The calculation is linear in \(m\), \(c_p\), and \(r\). A ±10% uncertainty in \(m\) or \(c_p\) produces a ±10% uncertainty in required power.
• Actual lamp-array electrical power must exceed the absorbed wafer power because of reflection, chamber-window absorption, and heat losses to the chamber; efficiencies are commonly well below 100%, so installed lamp power can be several times the absorbed power. That installed-power ratio is not estimated here because it requires equipment-specific optical/thermal loss data labeled needs primary source validation.
• The calculation explains why high-ramp RTP systems need large lamp banks and why SiC processes that also require high temperatures place even greater demand on chamber materials and cooling.

This calculation is illustrative; it does not prove any vendor’s system can achieve the stated ramp rate on a production wafer.

Unit economics / business model

Thermal-processing equipment is monetized primarily through system sales, not subscriptions or per-wafer royalties. The main revenue streams are:

1. System sales — single-wafer RTP or SiC anneal chambers sold to device manufacturers. Exact ASPs are not repeated here because they are not independently verified; typical advanced single-wafer thermal systems are reported in the multi-million-dollar range, but this must be labeled needs primary source validation.
2. Service and spares — lamps, quartz windows, thermocouples, pyrometers, showerheads/tubes, and preventive maintenance. This is recurring revenue for the equipment supplier.
3. Process support and upgrades — the supplier may assist with recipe development for high-temperature SiC anneal, especially during customer qualification.
4. Used/refurbished equipment — a secondary market exists, but it is not a primary value driver for the OEMs.

Applied Materials’ 10-K discloses a services/spares revenue stream as part of its overall business model, but segment-level thermal gross margin is not separated here [S4]. The value capture is asymmetric: the equipment OEM captures system ASP plus long-tail service; the device maker captures value only if the tool achieves yield/reliability in production. SiC annealing is a high-friction process step, so the equipment vendor’s process knowledge tends to increase switching costs, especially during customer qualification.

Disconfirming Evidence

The thesis that high-temperature SiC annealing is a durable, valuable equipment bottleneck would be weakened or invalidated if any of the following occurs:

1. Furnace technology improves to match RTP throughput and surface quality at >1,800 °C, eliminating the single-wafer RTP differentiation.
2. Laser annealing or microwave annealing displaces lamp/thermal annealing for SiC implant activation with lower thermal budget and equivalent yield.
3. SiC device architectures change such that implant activation anneal is no longer the yield-limiting step, for example through epitaxial channel/dopant engineering that reduces ion implantation or anneal requirements.
4. Customer qualification evidence shows that high-temperature SiC anneal systems fail in production on uniformity, repeatability, or cost-of-ownership metrics, contradicting vendor self-reported specs.
5. Public company filings show a material shift in capital spending away from thermal equipment or a loss of market share by the listed thermal-equipment suppliers to unlisted or non-US competitors.

Any one of these would require revisiting the economic and technology moat arguments above.