Industrial communication processors and protocol ICs

Working definition and scope

An industrial communication processor or protocol IC is a semiconductor device—PHY, MAC, switch, dual-port-memory slave controller, multiprotocol ASIC/ASSP, FPGA core, or software-programmable communication SoC—that terminates, switches, bridges, or accelerates industrial protocols. The important distinction from ordinary enterprise Ethernet silicon is the addition of hard real-time behavior: deterministic cycle times, synchronized clocks, priority-based arbitration, low forwarding jitter, and often hardware-level processing of process data frames.

The value chain is not a single standard. Felser’s peer-reviewed survey in Proceedings of the IEEE classifies real-time Ethernet approaches into distinct architectural classes: conventional TCP/IP-based communication, Ethernet systems that retain standard Ethernet but modify higher layers, and systems that modify Ethernet hardware or bypass standard MAC behavior for hard real-time forwarding [S1]. This distinction is foundational for understanding why an EtherCAT slave ASIC is architecturally different from an EtherNet/IP TCP/IP stack processor.

The protocol/IC stack

Industrial protocol ICs map to distinct OSI-like functions:

• Physical layer: industrial Ethernet PHYs, CAN/RS-485/IO-Link transceivers, HART modems. Texas Instruments sells devices such as the DP83826E 10/100 Ethernet PHY, positioned for low-latency industrial Ethernet [S8].
• Layer 2 switching and forwarding: TSN-enabled Ethernet switches, EtherCAT slave controllers, PROFINET IRT/RT forwarding hardware. NXP’s Ethernet switch portfolio includes TSN-capable industrial Ethernet switches [S10].
• Dedicated multiprotocol ASICs: ADI’s fido5000 is marketed as a multiprotocol real-time Ethernet switch supporting PROFINET RT/IRT, EtherNet/IP, EtherCAT, Sercos III, and POWERLINK [S9]. Microchip’s LAN9252 is an EtherCAT slave controller [S11].
• Communication processors/SoCs: application processors with integrated industrial MACs, EtherCAT slave controllers, CAN controllers, and software protocol stacks. STMicroelectronics promotes its STM32 families for industrial communication [S12].

The source-tier issue matters here: product pages such as [S8], [S9], [S10], and [S11] are Tier 2 self-reported marketing/technical documents. They establish product existence and vendor claims, not independent proof of deterministic performance. They should not be treated as equal to standards-body documents or peer-reviewed measurement papers.

Standards and protocol organizations

A standards or protocol-organization document is generally stronger than a vendor product brief. Key documents for this technology:

• IEEE 802.3-2018, “IEEE Standard for Ethernet,” defines the Ethernet MAC/PHY frame format, minimum frame size, preamble/SFD, and interframe gap used in the worked calculation below [S3].
• ISO 11898-1:2015 is the CAN data-link and physical-signalling standard [S4]. It is a Tier 1 standards-body document. CAN remains a major industrial/embedded protocol, especially for distributed real-time control and diagnostic traffic.
• EtherCAT Technology Group publishes the EtherCAT technology description, including slave processing-on-the-fly behavior [S5].
• ODVA maintains EtherNet/IP, the industrial Ethernet protocol derived from the Common Industrial Protocol [S6].
• PROFINET International maintains PROFINET [S7].
• IEEE 802.1 TSN documents enhancements to Ethernet: time synchronization, scheduled traffic, frame preemption, and redundancy [S18].

The existence of multiple independent organizations—ETG, ODVA, PI, IEEE 802.1—is itself evidence of fragmentation. “Industrial Ethernet” is not one homogeneous standard; buyers must select a protocol family and often a specific ASIC architecture per protocol [S1].

Granted-patent evidence

Source: United States granted patent US5001642A, Robert Bosch GmbH, “Method and apparatus for serial data communication,” granted 1991-03-19 [S2].

This is a granted utility patent, not a pre-grant application. It describes serial data communication with non-destructive contention resolution of the type used in CAN-style priority arbitration. The grant date and assignee are visible in the Google Patents record [S2]. The patent is useful as evidence of recorded claims in serial industrial communication, not as evidence that any current commercial product implementing CAN or CAN FD has a current patent moat. A 1991 grant is far beyond any reasonable patent-term exclusivity; no present-day competitive advantage can be inferred from this patent alone.

Important interpretive rule: a patent is a legal claim record. It does not prove that a product meets sub-microsecond latency, survives EMC tests, interoperates across vendor implementations, or achieved design wins. Those claims require measurement data, conformance certificates, or independent benchmarks.

Peer-reviewed evidence

Source: Max Felser, “Real-Time Ethernet—Industry Prospective,” Proceedings of the IEEE, vol. 93, no. 6, pp. 1118–1129, June 2005. DOI: 10.1109/JPROC.2005.849720 [S1].

This DOI identifies a peer-reviewed journal article in Proceedings of the IEEE. Felser’s article is old but foundational. It establishes:

• Industrial Ethernet is not a single protocol but a class of approaches.
• Some systems preserve TCP/IP and accept nondeterministic timing; others alter the stack; others modify Ethernet forwarding itself.
• Hard-real-time systems require repeatable cycle times and synchronism, not merely high throughput.

This is Tier 1 for the classification claim. Wherever the note relies on that classification, it is citation-bound to [S1]. It is not a Tier 2 vendor blog or anonymous benchmark.

Quantitative worked calculation: minimum Ethernet frame transmission time

The purpose of this calculation is to separate the deterministic floor imposed by Ethernet framing from any additional device latency introduced by a PHY, switch, or protocol ASIC.

Formula

\[

t_{frame} = \frac{(L_{frame} + L_{preamble/SFD} + L_{IFG}) \times 8\ \text{bits/byte}}{R}

\]

Where:

• \(L_{frame}\) = Ethernet frame size in bytes, excluding preamble/SFD.
• \(L_{preamble/SFD}\) = 8 bytes, per IEEE 802.3-2018 frame format [S3].
• \(L_{IFG}\) = 12 bytes minimum interframe gap for Ethernet [S3].
• \(R\) = nominal data rate in bits per second.

Calculation for minimum Ethernet frame

IEEE 802.3-2018 defines a minimum Ethernet frame of 64 octets [S3]. Therefore:

\[

L_{frame} = 64,\quad L_{preamble/SFD} = 8,\quad L_{IFG} = 12

\]

\[

\text{total octets} = 64 + 8 + 12 = 84\ \text{bytes}

\]

\[

\text{total bits} = 84 \times 8 = 672\ \text{bits}

\]

At 100 Mbit/s:

\[

t_{min,100M} = \frac{672}{100 \times 10^6} = 6.72\ \mu s

\]

At 1 Gbit/s:

\[

t_{min,1G} = \frac{672}{1 \times 10^9} = 0.672\ \mu s

\]

Sensitivity table

Derived inputs: 8-byte preamble/SFD and 12-byte IFG from [S3].

This calculation is a wire-time floor. It does not include store-and-forward memory latency, forwarding-table lookup, cut-through processing, PHY analog latency, or protocol-stack execution time. A vendor claim of, for example, “low-latency PHY” on [S8] or “multiprotocol real-time Ethernet switch” on [S9] must not be read as equivalent to the simple wire-time floor above. The additional device latency is product-specific and, unless independently measured, remains needs primary source validation.

Parameter table

Unit economics / business model

Who monetizes this technology:

1. Semiconductor vendors monetize via chip sales. Texas Instruments, Analog Devices, NXP, Microchip, STMicroelectronics, and others sell physical-layer devices, switches, slave controllers, and MCUs/SoCs with industrial protocol support. Product-level gross margin for a specific industrial protocol IC is not disclosed in SEC filings at that granularity. Therefore, any specific DP83826E or fido5000 product margin is needs primary source validation. TI’s 10-K and ADI’s 10-K are available via EDGAR [S15][S16], but they report consolidated and segment results, not protocol-IC product margins.

1. Protocol IP and ecosystem owners monetize via licensing/conformance ecosystems. EtherCAT slave controller IP and conformance are managed through the EtherCAT Technology Group [S5]; ODVA licenses EtherNet/IP conformance and related technology [S6]; PROFINET International administers PROFINET [S7]. These organizations are not public companies, and their licensing economics are not disclosed in the cited SEC filings.

1. Industrial equipment OEMs and networking vendors capture value by embedding protocol ICs into higher-priced control systems. Rockwell Automation sells EtherNet/IP-enabled controllers, drives, and I/O [S13]; Belden/Hirschmann sells industrial Ethernet switches [S14]. For these buyers, the protocol IC is a bill-of-materials input, not the revenue unit.

1. Software/protocol stack suppliers monetize stacks and commissioning tools, but no public US-listed pure-play protocol-stack vendor is cited in this note because none was used as a source.

Conclusion: the dominant monetization form is chip sale plus ecosystem licensing, with integration value captured downstream. Exact segment margins must be sourced from primary filings; the present note does not invent them.

Company-filing cross-reference and discrepancies

The source-base includes EDGAR 10-K lookup records for Texas Instruments, Analog Devices, and NXP [S15][S16][S17].

Marketing claim vs. filing risk language. Vendor product pages claim industrial readiness, deterministic operation, and multi-protocol support [S8][S9][S10][S11]. SEC filings, by contrast, contain forward-looking risk language about rapid technological change, standards evolution, competition, and design-win uncertainty. For example, semiconductor 10-Ks routinely state that future success depends on developing products that meet evolving customer and industry requirements; if standards change or products become obsolete, revenue may be harmed. The specific risk-factor language in each 10-K should be retrieved from [S15][S16][S17] and compared sentence-by-sentence with the product pages before treating a marketing latency or determinism claim as investible fact.

Observed discrepancy pattern:

• Product literature often uses terms such as “low latency,” “real-time,” and “multiprotocol” without publishing a third-party benchmark [S8][S9].
• SEC filings do not isolate the revenue, margin, or market share of industrial communication processors/protocol ICs from consolidated analog/mixed-signal or MCU/automotive segments [S15][S16][S17].
• Therefore, the technical narrative and the financial disclosure are at different levels of granularity. A researcher should not infer that a vendor’s industrial-protocol product line is independently material just because product pages exist; the 10-K business discussion often groups these products into broader segments.

Contradiction within the standards ecosystem: “Industrial Ethernet” is sometimes marketed as one category, but Felser [S1] and the existence of separate protocol organizations [S5][S6][S7] show incompatible protocol families. A single “industrial Ethernet” chip is not automatically interoperable across all ecosystems.

Disconfirming Evidence

The investment/thesis case for industrial communication processors and protocol ICs would be materially weakened if:

• Industrial Ethernet protocol fragmentation persists and no TSN profile becomes a broad design-win standard, forcing ASIC vendors to maintain costly multi-protocol designs without volume concentration [S1][S5][S6][S7][S18].
• Semiconductor vendor 10-K disclosures show weak or declining industrial/analog segment growth, confirming that product-level “industrial readiness” is not translating into financial disclosure [S15][S16][S17].
• Major OEMs reject dedicated EtherCAT/PROFINET-IRT ASICs in favor of software stacks on commodity Ethernet/MCU hardware, collapsing the protocol-ASIC pricing premium.
• Independent conformance or benchmark data contradict vendor claims of deterministic latency or interoperability on [S8][S9][S10][S11].
• Patents such as the cited CAN grant [S2] remain the only “moat” evidence, and continued lack of modern granted patents with current term indicates no durable IP barrier.
• Ethernet wire-time sensitivity shifts decisively toward non-issue because application cycle times rise substantially, reducing the value of sub-microsecond synchronization for most buyers.