Executive summary
Gate-all-around (GAA) transistors and backside power delivery networks (BSPDN) are two separate but now-converging scaling technologies for advanced logic. GAA replaces the FinFET fin with a stack of silicon nanosheets or nanowires fully surrounded by the gate. Backside power delivery moves the power-distribution network from the front of the wafer to the back, freeing routing resources for signals and allowing wider, lower-resistance metal rails.
The strongest evidence for GAA feasibility is the peer-reviewed IEDM 2017 paper by Loubet et al. showing stacked Si nanosheet transistors can extend scaling beyond FinFETs [S1]. IRDS 2022 argues these are system-level scaling levers [S2]. Company disclosures from Samsung, Intel, and TSMC are Tier 2 self-reported claims and must be cross-checked against SEC filings [S3][S4][S5][S6][S7]. A granted patent is evidence of allowed claims, not evidence of yield, performance, or commercial viability; any patent cited here must be treated that way.
Technology background
2.1 GAA transistor structure and electrostatic rationale
In a FinFET, the gate wraps three sides of a thin vertical fin. As gate length scales below roughly 12–15 nm, control of the channel degrades: drain-induced barrier lowering (DIBL) rises, subthreshold swing worsens, and leakage increases. GAA surrounds the silicon channel on all four sides, improving electrostatic integrity at short gate lengths.
Subthreshold swing is bounded by:
\[
SS = \frac{kT}{q}\ln 10 \left(1+\frac{C_d}{C_{ox}}\right)
\]
The ideal room-temperature limit when \(C_d \ll C_{ox}\) is about 60 mV/dec. GAA maximizes \(C_{ox}\) per footprint and reduces drain coupling, allowing operation closer to the ideal limit than FinFETs at the same gate length. Loubet et al. reported stacked nanosheet transistors with below-FinFET leakage and improved short-channel control [S1].
Key structural elements from the Loubet paper include:
- Vertically stacked Si nanosheets released by selective removal of sacrificial SiGe layers.
- Inner spacers to control gate-source/drain parasitic capacitance.
- A gate stack that surrounds each nanosheet on all four sides.
- Epitaxially merged source/drain regions.
IRDS 2022 lists gate-all-around nanosheet devices as a required evolutionary step in the “More Moore” roadmap, alongside buried power rails and backside power delivery [S2].
2.2 Backside power delivery (BSPDN)
Conventional chips route both power and signals on the frontside metal stack. Power rails occupy metal tracks that compete with signal wiring. As pitches shrink, frontside power rails become narrow and resistive, causing IR drop and routing congestion.
BSPDN moves power delivery to the backside of the wafer:
- Power rails are placed on the wafer backside after thinning.
- Through-silicon or backside vias connect the frontside transistors to the backside metal.
- Buried power rails can run under the transistor layer.
Intel’s implementation is marketed as PowerVia [S4]; imec has demonstrated backside power approaches for scalable logic [S8].
Source evidence and cross-checking
3.1 Tier 1 evidence
Peer-reviewed paper:
- Loubet et al., “Stacked Nanosheet Gate-All-Around Transistor to Enable Beyond FinFET Scaling,” IEDM 2017. DOI:
10.1109/IEDM.2017.8268383. This is a peer-reviewed conference paper with measured transistor data. It supports the feasibility claim that vertically stacked Si nanosheets can provide better electrostatic control than FinFETs at scaled dimensions [S1].
Standards-body roadmap:
- IEEE IRDS 2022 More Moore. IRDS is produced by IEEE volunteers; it is a standards-body-class roadmap document. It places GAA, buried power rails, and backside power delivery on the scaling roadmap [S2].
Granted patent candidate:
- US 11,264,510 B2, “Backside power delivery for integrated circuit devices,” Intel Corp., granted 2022-03-08. Identifier resolution needs primary source validation. Even if valid, this is evidence of a recorded claim, not proof that Intel achieved commercial PowerVia yield or performance [S9].
A second patent candidate is Samsung’s US 10,566,567 B2, “Semiconductor device,” granted 2020-02-18. Identifier resolution needs primary source validation. Use only as a patent-class reference, not a performance source [S10].
Discipline note: A peer-reviewed paper with measured transistors is stronger than a patent for “is this feasible?”. A standards-body roadmap is stronger for “what does the industry expect next?”. A patent is strongest only for “what claims does an assignee own?”.
3.2 Company disclosures and cross-checks
Samsung announced 3 nm GAA mass production on 2022-06-30. The press release claims 45% lower power, 23% higher performance, and 16% smaller area compared with 5 nm FinFET, all self-reported [S3]. These numbers are not independently verified in the same release, and Samsung did not provide yield data. Treat as Tier 2 self-reported marketing.
Intel’s PowerVia announcement claims backside power delivery enables higher frequency and density; Intel separately disclosed it demonstrated a 6% frequency gain in a test chip, self-reported [S4]. Intel’s 10-K risk factor language is much more cautious: process-technology transitions may be delayed, may not achieve expected performance, and may require costly redesigns [S6]. That is the expected discrepancy between marketing and filed disclosure.
TSMC’s technology page describes its N2 nanosheet node and relative speed/power trade-offs, but it does not disclose yield or BSPDN-specific commercial metrics [S5]. TSMC’s 20-F discusses advanced-node ramp and capital intensity at a high level, not per-node yield [S7].
Quantitative worked calculation: frontside vs. backside rail IR drop
Question: How much can a backside power rail reduce voltage drop compared with a frontside rail of the same length?
Formula:
\[
R = \frac{\rho L}{W t}
\]
\[
\Delta V = I R
\]
Where:
- \(R\) = resistance
- \(\rho\) = bulk Cu resistivity
- \(L\) = rail length
- \(W\) = rail width
- \(t\) = rail thickness
- \(I\) = current per local rail
Inputs:
| Parameter | Value | Unit |
|---|---|---|
| Bulk Cu resistivity, \(\rho\) | 1.68 | µΩ·cm |
| Rail length, \(L\) | 10 | µm |
| Frontside rail width, \(W_f\) | 32 | nm |
| Frontside rail thickness, \(t_f\) | 40 | nm |
| Backside rail width, \(W_b\) | 100 | nm |
| Backside rail thickness, \(t_b\) | 120 | nm |
| Current per rail, \(I\) | 1 | mA |
Conversion and area:
- \(L = 10 \,\mu m = 0.001 \,cm\)
- \(\rho = 1.68 \times 10^{-6} \,\Omega{\cdot}cm\)
- Frontside cross-section: \(W_f t_f = 32 \times 40 = 1280 \,nm^2 = 1.28 \times 10^{-11} \,cm^2\)
- Backside cross-section: \(W_b t_b = 100 \times 120 = 12000 \,nm^2 = 1.20 \times 10^{-10} \,cm^2\)
Frontside resistance:
\[
R_f = \frac{1.68 \times 10^{-6} \times 0.001}{1.28 \times 10^{-11}}
= 131.25 \,\Omega
\]
Backside resistance:
\[
R_b = \frac{1.68 \times 10^{-6} \times 0.001}{1.20 \times 10^{-10}}
= 14.0 \,\Omega
\]
Voltage drop at 1 mA:
\[
\Delta V_f = 0.001 \times 131.25 = 0.1313 \,V
\]
\[
\Delta V_b = 0.001 \times 14.0 = 0.0140 \,V
\]
Reduction:
\[
0.1313 - 0.0140 = 0.1173 \,V
\]
The backside rail reduces IR drop by 89% in this simplified example, with a resistance ratio of 9.4×.
Sensitivity:
- If frontside width/thickness is ±20%, \(R_f\) ranges from about 109 Ω to 164 Ω, so \(\Delta V_f\) ranges from 0.109 V to 0.164 V.
- If backside width/thickness is ±20%, \(R_b\) ranges from about 11.7 Ω to 17.5 Ω, so \(\Delta V_b\) ranges from 0.012 V to 0.018 V.
- If effective Cu resistivity doubles in narrow frontside lines due to barrier/liner and surface-scattering effects, \(R_f\) becomes about 262.5 Ω and \(\Delta V_f\) becomes 0.2625 V. Backside lines are wider and may suffer less from the same size-effect penalty, so the benefit could be larger.
- At 2 mA per rail, voltage drops double: 0.263 V frontside vs. 0.028 V backside.
Caveat: Real BSPDN includes via resistance, contact resistance, decoupling capacitance placement, wafer-thinning cost, and thermal constraints. The calculation shows the first-order interconnect benefit, not a full pathfinding result. Rail dimensions are assumed from published BSPDN concepts; they are not a direct measurement from any single source.
Parameter table
| Parameter | Value | Source | Tier | Measured/derived/assumed/inferred | Cross-verified |
|---|---|---|---|---|---|
| Subthreshold swing ideal | ~60 mV/dec | [S1] | 1 | Derived from physics | Yes, formula |
| GAA electrostatic control | Better than FinFET at scaled gate length | [S1] | 1 | Measured transistor data | Single-source |
| GAA roadmap placement | More Moore scaling path | [S2] | 1 | Standards-body roadmap | Yes, industry standard |
| Samsung 3 nm GAA power reduction vs 5 nm | 45% self-reported | [S3] | 2 | Self-reported marketing | No; needs primary source validation |
| Samsung 3 nm GAA performance gain vs 5 nm | 23% self-reported | [S3] | 2 | Self-reported marketing | No; needs primary source validation |
| Intel PowerVia frequency gain | 6% self-reported | [S4] | 2 | Self-reported tech test | No; needs primary source validation |
| Frontside rail width | 32 nm | Assumed from BSPDN concepts | 2/assumed | Assumed | No |
| Frontside rail thickness | 40 nm | Assumed from BSPDN concepts | 2/assumed | Assumed | No |
| Backside rail width | 100 nm | Assumed from BSPDN concepts | 2/assumed | Assumed | No |
| Backside rail thickness | 120 nm | Assumed from BSPDN concepts | 2/assumed | Assumed | No |
| Bulk Cu resistivity | 1.68 µΩ·cm | Standard materials data | 1/standard | Measured reference value | Yes, standard |
| IR drop reduction | 9.4×, 89% | Derivation in §4 | Derived | Derived from formula | No measurement |
Unit economics / business model
Who monetizes this technology?
- Foundries — TSMC, Samsung Foundry, and Intel Foundry monetize GAA/BSPDN through advanced-node wafer sales and design-enablement/NRE. TSMC’s 20-F discloses that wafer sales are the core revenue model and advanced nodes carry high capital intensity [S7]. Per-wafer prices for N2/3 nm are not separately disclosed; any widely quoted dollar figure is needs primary source validation.
- EDA and IP vendors — Synopsys and Cadence license tools and IP for GAA and backside power/thermal signoff. Their exposure is indirect but real: GAA forces standard-cell and power-grid re-architecture.
- Equipment and materials suppliers — ASML, Applied Materials, Lam Research, KLA sell lithography, deposition/etch, and metrology tools capable of nanosheet release, inner spacers, backside via alignment, wafer bonding, and thinning.
- Chip designers and system companies — Fabless customers capture value through better performance per watt and lower IR drop, but they pay for it in higher wafer/NRE costs.
Value capture is not evenly distributed. The foundry with a working GAA/BSPDN node has pricing leverage. The equipment suppliers benefit before yield is proven because advanced R&D lines require tools regardless of customer chip volume. Patent owners do not automatically capture revenue unless a license or litigation strategy exists.
Disconfirming evidence
The GAA/BSPDN thesis would weaken or fail if:
- No measured yield curve: Samsung or TSMC fails to disclose sustained advanced-node GAA yield at commercial economics.
- Backside power costs exceed benefits: Wafer thinning, backside alignment, and thermal management costs make BSPDN net neutral or negative for power and area.
- GAA electrostatic advantage disappears at system level: If standard-cell height, interconnect, and parasitics eliminate the transistor-level gains claimed in [S1].
- Customer adoption stalls: Fabless customers stay on older FinFET nodes longer because GAA/BSPDN design complexity or NRE outweighs power/performance gains.
- Patent evidence is invalidated: The candidate patent claims are not usable or are proven invalid/narrow; patent ownership is then not a moat.
- IRDS roadmap changes: A future IRDS edition removes GAA/BSPDN as a required path or replaces it with a superior architecture.