Executive summary
Semiconductor metrology and inspection are the process-control feedback loop that converts fab data into yield. Advanced nodes cannot be yielded without in-line dimensional control: an excursion that survives a few days at leading-edge wafer value can destroy tens of millions of dollars of product. The economic logic is simple in structure but hard to prove in any single quarter: inspection and metrology tools are capital equipment with high sticker prices and meaningful service costs, while their benefit is a probability of avoiding yield loss, not a guaranteed cost save.
This note covers the technology first—optical inspection, e-beam inspection, scatterometry/optical critical dimension (OCD), CD-SEM, and overlay metrology—and then builds a unit-economics model around a generic process-control tool. The worked calculation shows that, under stated assumptions, a $8M inspection tool inspecting 20% of wafers costs roughly $1.37 per produced wafer, and must prevent about 0.13% monthly yield loss at a $8,000 wafer ASP to break even. All dollar inputs are assumptions unless validated against primary filings.
The most important structural observations:
- Inspection and metrology are not interchangeable. Inspection finds defects; metrology measures dimensions and overlay. Different economics; different suppliers.
- The economic value is option value. A process-control tool is a hedge against yield excursions, not a direct throughput cost.
- Patents are evidence of recorded claims, not proof of performance. The patent cited here, US 7,639,896 B2, claims an angular-resolved scatterometry apparatus. It does not demonstrate commercial throughput, accuracy at a customer site, or customer ROI.
- Vendor product pages quote best-case throughput. Realized utilization is lower. This is the single largest sensitivity in the cost-per-wafer calculation.
Technology deep-dive
2.1 Inspection versus metrology
Inspection tools detect physical anomalies: particles, residues, pattern defects, pits, scratches, bridging, or missing features. Metrology tools measure geometric or material properties: critical dimension (CD), sidewall angle, film thickness, overlay, composition, and stress. The two categories are often bundled by suppliers under “process control,” but the performance requirements and economic trade-offs are distinct.
The National Institute of Standards and Technology maintains program pages for critical-dimension metrology and semiconductor metrology, describing CD measurements at the nanometer scale as essential to controlling semiconductor fabrication processes (NIST Critical Dimension Metrology program page, accessed 2026-05-09). This is a Tier 1 standards-body source because NIST is a national metrology institute.
A peer-reviewed review, Madsen and Hansen, “Scatterometry—fast and robust measurements of nano-textured surfaces,” Surface Topography: Metrology and Properties, 4(2), 023003, 2016, DOI 10.1088/2051-672X/4/2/023003 (accessed 2026-05-09), states that scatterometry is used for fast, non-destructive characterization of nanostructured surfaces, including semiconductor grating structures. This paper provides the core optics/math basis for one branch of metrology.
2.2 Optical wafer inspection
Broadband plasma optical inspection is the incumbent high-throughput method in semiconductor fabs. Vendors describe their product families as being used for pattern defect inspection at advanced nodes. For example, KLA’s inspection product family page describes optical inspection platforms for patterned wafers (KLA product page, accessed 2026-05-09). This is Tier 2 self-reported marketing material.
The economic tension is resolution versus throughput. Optical inspection throughput is high, but defect sensitivity is limited by the diffraction limit and wafer noise. The transition to extreme ultraviolet (EUV) lithography and new materials intensifies the need for defect sensitivity at ever-smaller dimensions.
2.3 E-beam inspection
Electron-beam inspection offers higher resolution than optical inspection but is throughput-constrained because electron-beam imaging is serial or semi-parallel. Applied Materials markets an e-beam review platform, SEMVision G10, for defect review and classification (Applied Materials SEMVision G10 product page, accessed 2026-05-09). This is also Tier 2 self-reported.
The economic implication is that e-beam tools tend to be used for sampled inspection, engineering analysis, and defect review rather than 100% inline wafer inspection at high volume. The throughput gap between photon-based and electron-based techniques is the most important physical driver of sampling economics. This statement is [SINGLE-SOURCE] if only vendor marketing pages are available for throughput; it requires an independent benchmark or standard for full verification.
2.4 Scatterometry / optical critical dimension (OCD)
Scatterometry measures light diffracted from periodic structures and solves an inverse problem to infer CD, sidewall angle, film thickness, or overlay. It is fast, non-destructive, and compatible with in-line use, but it is model-based: the measured intensity is fitted to a model of the structure.
A granted patent covering angular-resolved scatterometry provides a legal record of the apparatus:
- Patent number: US 7,639,896 B2
- Title: Method and apparatus for angular-resolved spectroscopic lithography characterization
- Assignee: ASML Netherlands B.V.
- Grant date as printed: 2009-12-29 (needs primary source validation before formal reliance)
- URL: [patents.google.com (accessed 2026-05-09)
This is a Tier 1 source for claimed invention only. It is a granted patent, not an application. The distinction matters: a granted patent has survived patent-office examination, but it is still a record of claims, not proof of metrology accuracy, field reliability, or customer ROI. The peer-reviewed paper by Madsen and Hansen, from a different institution, supports the general measurement technique using scatterometry (DOI link).
These two sources—ASML patent and University/technical-institute review paper—are from different institutional lineages and therefore provide at least two independent sources for the load-bearing technical claim that angular-resolved scatterometry is an apparatus/method for characterizing nanostructures. The patent claims structure; the paper reviews method and application.
2.5 Overlay metrology and integrated metrology
Overlay error—the alignment accuracy between successive lithographic layers—is a yield killer. Overlay metrology can be performed by scatterometry or by imaging-based methods. ASML, the dominant lithography supplier, integrates metrology sensors directly on its lithography systems, so that certain measurements occur on the tool itself rather than on standalone metrology tools.
The ASML 20-F annual report describes lithography systems with alignment and level sensors and services (ASML SEC EDGAR 20-F search, accessed 2026-05-09). This is Tier 2 adoption/deployment context. The integration of metrology into lithography is a potential threat to standalone metrology suppliers if it cannibalizes certain standalone measurement steps, but also creates additional data streaming and software/service revenue.
2.6 Machine learning and data-driven process control
Multiple vendors now describe machine-learning-based defect classification within their product pages. For example, the Applied Materials SEMVision G10 page mentions classification capabilities. This is Tier 2 self-reported marketing and should be treated as such. No peer-reviewed performance benchmark is cited in this note because none was retrieved.
Cross-reference to filings: Company risk-factor language in the KLA 10-K and Applied Materials 10-K generally describes process-control products as complex and sensitive to customer yield requirements, but does not make quantitative throughput claims comparable to product pages (KLA 10-K EDGAR search; Applied Materials 10-K EDGAR search, accessed 2026-05-09). The discrepancy, if any, is that vendor product pages are explicit about performance under optimum conditions, while 10-K filings are deliberately cautious about variability. No quantitative contradiction is asserted without primary extraction.
Unit economics / business model
3.1 Who monetizes
Publicly traded process-control suppliers monetize this technology through:
- KLA Corporation (KLAC): sells standalone inspection and metrology systems, plus service, spares, and software. KLA’s 10-K describes revenue from products and services; the exact product/service split and gross margin require extraction from the filing (KLA 10-K EDGAR search, accessed 2026-05-09).
- Applied Materials (AMAT): sells process diagnostics and e-beam review products, plus broad semiconductor equipment and services (AMAT 10-K EDGAR search, accessed 2026-05-09).
- ASML (ASML): monetizes integrated metrology through lithography system sales and field service; the patent cited above is assigned to ASML (US 7,639,896 B2; ASML 20-F EDGAR search).
The business model is predominantly capital equipment sale plus recurring service/software. Margins are typically high for semiconductor equipment companies, but exact figures need primary source validation. No specific margin figure is reproduced here to avoid fabrication.
3.2 Who captures value
The economic value is split among:
- Tool suppliers: capture margin on capital equipment and service.
- Fab customers: capture avoided yield loss and improved time-to-yield.
- Third-party software/analytics: potentially capture incremental value through yield-management software, but no separately named buyer or supplier is asserted here.
3.3 Capital intensity and cyclicality
SEC 10-K filings for KLA, AMAT, and ASML all describe semiconductor capital-spending cyclicality as a risk factor. Process-control spending is also tied to technology transitions: smaller nodes, EUV adoption, advanced packaging, and new materials increase metrology/inspection intensity.
Worked calculation: cost per inspected wafer and break-even yield impact
The formula is:
\[
C_{\text{wafer}} = \frac{A + O + V}{W}
\]
\[
A = C_{\text{capex}} \times \frac{1-r}{L}
\]
\[
O = m \times C_{\text{capex}}
\]
\[
V = c \times W
\]
\[
W = T \times U \times H
\]
where:
- \(C_{\text{wafer}}\) = fully burdened cost per inspected wafer ($)
- \(A\) = annual depreciation ($/year)
- \(O\) = annual maintenance and labor ($/year)
- \(V\) = annual consumables ($/year)
- \(W\) = annual inspected wafers
- \(C_{\text{capex}}\) = tool purchase price ($)
- \(r\) = residual value fraction
- \(L\) = depreciation life (years)
- \(m\) = maintenance/labor cost as fraction of capex per year
- \(c\) = consumables cost per inspected wafer ($/wafer)
- \(T\) = throughput (wafers/hour)
- \(U\) = utilization fraction
- \(H\) = hours per year (8,760)
If the tool inspects a fraction \(s\) of produced wafers, the cost per produced wafer is:
\[
C_{\text{produced}} = s \times C_{\text{wafer}}
\]
5.1 Baseline inputs
| Parameter | Value | Source | Tier | Status | Cross-verified? |
|---|---|---|---|---|---|
| \(C_{\text{capex}}\) | $8,000,000 | Assumed from semiconductor-process-control tool class; not itemized in SEC filings | 2 | assumed | no — needs primary source validation |
| \(r\) | 10% | Assumed typical equipment residual | 2 | assumed | no |
| \(L\) | 5 years | Assumed typical depreciation life for semiconductor equipment | 2 | assumed | no |
| \(m\) | 12% | Assumed service/labor burden | 2 | assumed | no |
| \(c\) | $0.35/wafer | Assumed; not separately disclosed by suppliers | 2 | assumed | no |
| \(T\) | 60 wafers/hour | Vendor product-page best-case throughput; KLA inspection family page (URL) | 2 self-reported | assumed | single-source |
| \(U\) | 70% | SEMI E10 utilization convention (SEMI E10 product page) | 1 standard | assumed convention | no |
| \(H\) | 8,760 hours | Calendar hours | 1 | derived | yes |
| \(s\) | 20% | Assumed sampling rate | 2 | assumed | no |
5.2 Baseline calculation
\[
A = 8{,}000{,}000 \times \frac{0.90}{5} = 1{,}440{,}000 \text{ per year}
\]
\[
O = 0.12 \times 8{,}000{,}000 = 960{,}000 \text{ per year}
\]
\[
W = 60 \times 0.70 \times 8{,}760 = 367{,}920 \text{ wafers/year}
\]
\[
V = 0.35 \times 367{,}920 = 128{,}772 \text{ per year}
\]
\[
\text{Total annual cost} = 1{,}440{,}000 + 960{,}000 + 128{,}772 = 2{,}528{,}772
\]
\[
C_{\text{wafer}} = \frac{2{,}528{,}772}{367{,}920} \approx \$6.87
\]
\[
C_{\text{produced}} = 0.20 \times 6.87 \approx \$1.37
\]
Under baseline assumptions, the inspection cost is $6.87 per inspected wafer and $1.37 per produced wafer at 20% sampling.
5.3 Sensitivity
- If throughput falls to 40 wafers/hour: \(W = 245{,}280\); total annual cost = \(1{,}440{,}000 + 960{,}000 + 85{,}848 = 2{,}485{,}848\); \(C_{\text{wafer}} = \$10.13\); \(C_{\text{produced}} = \$2.03\).
- If utilization falls to 50% and throughput is 40 wafers/hour: \(W = 175{,}200\); total annual cost = \(1{,}440{,}000 + 960{,}000 + 61{,}320 = 2{,}461{,}320\); \(C_{\text{wafer}} = \$14.05\); \(C_{\text{produced}} = \$2.81\).
- If capex rises to $12M: \(A = 2{,}160{,}000\); \(O = 1{,}440{,}000\); \(V = 128{,}772\); total = \(3{,}728{,}772\); \(C_{\text{wafer}} = \$10.13\); \(C_{\text{produced}} = \$2.03\).
- If sampling rises to 100% at baseline: \(C_{\text{produced}} = \$6.87\).
The largest levers are throughput, utilization, and sampling fraction. Tool purchase price matters, but annualized cost is amortized over hundreds of thousands of wafers.
5.4 Break-even yield impact
To justify the annualized process-control cost, we calculate the minimum yield loss the tool must prevent:
\[
\Delta y_{\text{break-even}} = \frac{\text{Total annual cost}/12}{N_{\text{wspm}} \times R_{\text{wafer}}}
\]
Where:
- \(N_{\text{wspm}} = 20{,}000\) wafer starts per month (assumed mid-volume advanced fab)
- \(R_{\text{wafer}} = \$8{,}000\) revenue per wafer (assumed; needs primary source validation)
\[
\Delta y_{\text{break-even}} = \frac{2{,}528{,}772 / 12}{20{,}000 \times 8{,}000}
\]
\[
= \frac{210{,}731}{160{,}000{,}000}
\]
\[
\approx 0.00132 = 0.132\%
\]
So under these assumptions, a $8M inspection tool that prevents a sustained 0.14% monthly yield loss pays for itself before assigning any value to time-to-yield acceleration, scrap reduction, or excursion-avoidance beyond one month. This is the economic threshold a fab buyer implicitly uses, though actual decisions also include cycle time, learning rate, and process-window expansion.
Important caveat: All dollar inputs are assumptions. The calculation is arithmetic, not sourced financial data. It shows the structure of the economics, not a verified cost from any fab or supplier.
Contradictions and source-bound claims
6.1 Patent claims vs. commercial performance
US 7,639,896 B2 is a granted patent. It is evidence that ASML recorded a claim to an angular-resolved scatterometer. It is not evidence that the described system achieves a specific throughput, resolution, accuracy, or yield benefit in a customer fab. This distinction is essential for moat analysis: patent citations support innovation lineage, not product viability.
6.2 Vendor marketing vs. filed risk factors
Vendor product pages describe best-case throughput and application breadth. SEC filings for KLA, AMAT, and ASML discuss demand cyclicality, customer concentration, product complexity, and competitive risk. The two source classes answer different questions: product pages say what a tool can do under optimal conditions; 10-Ks say what could go wrong for the supplier. A moat claim built only on product-page throughput is weaker than one built on gross-margin durability and repeat revenue from service.
6.3 Scatterometry accuracy vs. model assumptions
Scatterometry is model-based. The Madsen and Hansen review describes fast, non-destructive measurement, but the accuracy of OCD depends on model selection and parameter regularization. This is a known limitation in the technical literature and affects the economics: inaccurate metrology can drive false yield decisions.
Disconfirming Evidence
The thesis that inspection/metrology economics are structurally attractive would be wrong if:
- Integrated metrology inside lithography tools replaces standalone measurements faster than standalone suppliers offset with software/services, shrinking the standalone process-control market.
- Machine-learning-based virtual metrology reduces the need for physical measurements, collapsing the wafer-throughput case for dedicated metrology tools.
- Throughput and utilization do not improve enough to make the cost per produced wafer acceptable as node sizes shrink and wafer ASPs in memory remain low.
- Yield entitlement saturates: if advanced fabs reach a point where incremental inspection adds negligible yield improvement, tool spending shifts to other productivity levers.
- Secular process-control intensity declines in absolute dollars per wafer start, which would contradict the technology-transition logic seen in current vendor product pages and SEC filings.
Any future source showing falling process-control revenue per wafer start, or a customer shifting to integrated-only measurement, would be an early disconfirming signal.