OSAT & Advanced Packaging

Scope and definitions

This note covers outsourced semiconductor assembly and test (OSAT) and the adjacent advanced packaging technology stack: fan-out wafer/panel-level packaging, 2.5D silicon interposers, embedded multi-die interconnect bridges, 3D stacking, chiplets, and hybrid/direct bonding.

“OSAT” is the service model: a fabless chip company or IDM sends finished wafers to an external provider for bumping, redistribution-layer formation, die placement, wirebonding or flip-chip attach, encapsulation, substrate attach, and final test. Advanced packaging is the technology challenge inside that model: redistributing I/O, integrating heterogeneous dies, and managing thermal-mechanical stress.

The main technical families researched here:

• Fan-out wafer-level packaging (FOWLP) — die is embedded in mold compound and an RDL redistributes I/O beyond the die edge, reducing substrate complexity.
• 2.5D silicon interposer / CoWoS — multiple dies, usually logic plus high-bandwidth memory, mounted on a silicon interposer with through-silicon vias.
• Embedded multi-die interconnect bridge (EMIB) — small silicon bridge embedded in an organic substrate to connect dies locally.
• Chiplet interconnect standards — UCIe-defined die-to-die PHY and physical interface.
• Hybrid bonding / direct Cu-Cu bonding — dielectric-to-dielectric and metal-to-metal bonding without traditional solder bumps.
• OSAT back-end test and assembly — test program development, burn-in, system-level test, package qualification.

Patent anchor: granted patent, not application

A granted US patent is cited here to demonstrate that fan-out packaging IP is recorded and assigned, not to prove commercial yield, reliability, or market adoption.

Source S1 — granted patent:

USPTO patent 9,472,536 B2 (Google Patents URL: https://patents.google.com/patent/US9472536B2/en), granted 2016-10-18, accessed 2026-04-28.

This is labeled as a granted patent, not a publication or application. The important analytical point: a granted patent is evidence that a specific set of claims was examined and recorded. It is not independent evidence that the described fan-out package is commercially produced at scale, that it meets reliability targets, or that the assignee captures economic value from the claims. The patent therefore supports “IP exists in fan-out packaging” but does not, by itself, support a moat claim.

This note deliberately avoids using the patent’s exact claim language because the claim text was not retrieved in full during this research pass. The patent is used only at the coarse level: “granted fan-out/advanced-package IP exists.” A deeper second-pass review should retrieve the claims and construction history if the goal is to assert freedom-to-operate or a specific technical moat.

Peer-reviewed paper anchor

Source S2 — peer-reviewed journal article:

King-Ning Tu, “Reliability challenges in 3D IC packaging technology,” Microelectronics Reliability, 2011, DOI 10.1016/j.microrel.2010.09.031, URL https://doi.org/10.1016/j.microrel.2010.09.031, accessed 2026-04-28.

This is a peer-reviewed journal article, not a preprint. It is used for reliability physics and for the load-bearing claim that 3D packaging introduces mechanical, thermal, and electrical reliability failure modes distinct from monolithic silicon. Specific failure modes discussed in the cited literature include:

• electromigration and current crowding in micro-bumps and solder joints;
• void formation and intermetallic-compound growth at interfaces;
• thermal stress generated by coefficient-of-thermal-expansion mismatches between silicon, underfill, mold compound, and substrate;
• TSV stress and keep-out-zone concerns.

This is a Tier 1 source for reliability claims. It is not used to estimate any market number.

Standards-body anchor

Two standards/industry specifications are used.

Source S3 — UCIe specification (Tier 2, industry consortium, not IEEE/ISO):

UCIe 1.1 specification, UCIe Consortium, URL https://www.uciexpress.org/specification, accessed 2026-04-28. UCIe public materials define die-to-die interconnect with distinct “standard” and “advanced package” physical options. It is an industry consortium document, so it is a step below a formal IEEE/ISO/JEDEC standard, but it is a primary source for the chiplet interface trend.

Source S4 — JEDEC standard (Tier 1 standards body):

JEDEC JESD235, High Bandwidth Memory DRAM standard, URL https://www.jedec.org/standards-documents/docs/jesd235, accessed 2026-04-28. HBM is the most important volume driver for 2.5D silicon interposers and TSV supply because HBM stacks require extremely dense die-to-die I/O and are assembled beside or on the same interposer as the logic die. JEDEC JESD235 is an authoritative standards-body document.

Company technical documents and filings

The following Tier 2 company technical pages are cited as self-reported technical/positioning claims, not independent validation:

• S5 — TSMC CoWoS page: https://www.tsmc.com/english/dedicatedFoundry/services/cowos.htm, accessed 2026-04-28. Self-reported description of TSMC’s 2.5D/3D packaging family.
• S6 — Intel EMIB/Foveros page: https://www.intel.com/content/www/us/en/architecture-and-technology/emib.html, accessed 2026-04-28. Self-reported description of Intel’s embedded bridge and 3D stacking.
• S7 — ASE VIPack page: https://ase.aseglobal.com/en/technology/vipack, accessed 2026-04-28. Self-reported OSAT advanced packaging platform.

Primary company filings used for buyer and economic context:

• S8 — Amkor Technology Form 10-K, FY2023: EDGAR CIK 0001047127, URL https://www.sec.gov/cgi-bin/browse-edgar?action=getcompany&CIK=0001047127&type=10-K&dateb=&owner=include&count=40, accessed 2026-04-28.
• S9 — TSMC Form 20-F, FY2023: EDGAR CIK 0001046179, URL https://www.sec.gov/cgi-bin/browse-edgar?action=getcompany&CIK=0001046179&type=20-F&dateb=&owner=include&count=40, accessed 2026-04-28.

Additional 10-K/20-F EDGAR company pages are listed in the Sources section for ticker connections and buyer identification.

Cross-reference of technical marketing claims against filings

There is a recurring discrepancy of tone, not necessarily falsehood, between technical marketing pages and risk-factor disclosures.

TSMC example:

The TSMC CoWoS page presents CoWoS as a production packaging family for high-performance computing and AI accelerators [S5]. The same company’s 20-F risk factors, available via EDGAR [S9], emphasize capital-intensive capacity expansion, technology transition risk, customer concentration, and the fact that demand for advanced packaging may not fully utilize expanded capacity if end-market demand shifts. This is not a direct contradiction; it is a materiality warning that should temper any “CoWoS capacity is a guaranteed moat” conclusion.

Amkor example:

Amkor’s technical materials and investor materials discuss advanced packaging as a growth area and the company presents itself as a leading OSAT with advanced-package capability [S7, S8]. Its Form 10-K risk factors disclose reliance on a limited number of large customers, volatility in mobile and automotive demand, and the high capital cost of advanced packaging lines [S8]. The disclosures imply that advanced-package revenue is not a low-risk annuity; it is concentrated, cyclical, and capital-intensive.

Worked calculation: area-array micro-bump density and pitch sensitivity

One load-bearing quantitative assertion from the UCIe-oriented packaging literature is that fine-pitch micro-bump or hybrid-bond interconnects increase die-to-die I/O density, but they also raise alignment, stress, and test burden [S2][S3].

Formula

For an area array of interconnects on a square pitch \(p\) µm:

\[

D = \frac{1}{(p/1000)^2} = \frac{10^6}{p^2} \quad \text{interconnects/mm}^2

\]

Inputs

• \(p = 55\ \mu\text{m}\): typical standard-package or coarse advanced-package pitch used here as a baseline.
• \(p = 45\ \mu\text{m}\): UCIe advanced-package nominal pitch used in this calculation; this should be treated as single-source from the UCIe public specification [S3] until the spec document itself is retrieved and the exact pitch value is validated.
• \(p = 35\ \mu\text{m}\): finer-pitch sensitivity case.

Calculation

For \(p = 55\ \mu\text{m}\):

\[

D_{55} = \frac{10^6}{55^2} = \frac{10^6}{3025} = 330.6\ \text{interconnects/mm}^2

\]

For \(p = 45\ \mu\text{m}\):

\[

D_{45} = \frac{10^6}{45^2} = \frac{10^6}{2025} = 493.8\ \text{interconnects/mm}^2

\]

For \(p = 35\ \mu\text{m}\):

\[

D_{35} = \frac{10^6}{35^2} = \frac{10^6}{1225} = 816.3\ \text{interconnects/mm}^2

\]

Sensitivity

Pitch shrink from 55 µm to 45 µm:

\[

\frac{D_{45}}{D_{55}} = \left(\frac{55}{45}\right)^2 = 1.4938

\]

That is a +49.4% area-density increase.

Pitch shrink from 45 µm to 35 µm:

\[

\frac{D_{35}}{D_{45}} = \left(\frac{45}{35}\right)^2 = 1.6531

\]

That is a +65.3% area-density increase.

Practical interpretation

A 10 mm × 10 mm area at 45 µm pitch contains roughly:

\[

493.8\ \text{mm}^{-2} \times 100\ \text{mm}^2 = 49,380\ \text{interconnects}

\]

At 35 µm pitch, the same area contains roughly:

\[

816.3\ \text{mm}^{-2} \times 100\ \text{mm}^2 = 81,630\ \text{interconnects}

\]

The density gain is real, but it is not free. Peer-reviewed reliability work [S2] identifies thermal stress, current crowding, and interface failure as the limiting physics at fine pitch. Therefore, the pitch-density calculation should not be read as proof that all of those interconnects are usable without additional reliability margin, test access, or thermal management.

Parameter table

Unit economics / business model

Who monetizes this technology:

1. Foundry + advanced packaging bundle. TSMC monetizes CoWoS/InFO/SoIC as a follow-on service attached to wafer fabrication. The economic model is effectively “sell the wafer, sell the package, sell the yield/access.” TSMC does not isolate advanced-packaging revenue in its 20-F; TSMC’s overall FY2023 gross margin was 54.4% company-wide [S9]. That company-wide margin is not the same as packaging-only margin; packaging-only margin is not disclosed in the cited filing and is needs primary source validation.

1. OSAT assembly and test service. Amkor and ASE monetize packaging and test as a service: customer-owned die or wafers are assembled and tested for a per-unit or per-program fee. Amkor’s 10-K shows a mid-teens gross-margin structure [S8], with high materials content and capital intensity. The exact FY2023 gross margin should be recalculated from the income statement in the filing; the “mid-teens” figure is a ballpark drawn from the filed financials, not an independent estimate.

1. Equipment suppliers. Advanced packaging requires dedicated lithography-like exposure tools, dielectric deposition, copper plating, etch, CMP, die bonders, thermocompression bonders, inspection, and metrology. Equipment suppliers are monetized through tool sales, service agreements, and consumables; no specific margin figure is asserted here because this note did not retrieve their 10-K income statements for packaging-specific revenue.

1. Materials and substrate suppliers. Organic substrates, RDL polymers, plating chemicals, mold compound, and underfill are the recurring materials spend. These are tied to package volume, not chip design wins.

Who captures the value:

The highest value capture is likely the foundry bundle because it controls the leading-edge package architecture and capacity; the OSATs capture service value but face customer concentration and price competition; equipment suppliers capture capital-expenditure value before capacity is built. This is an inference from the cited filings, not a sourced market-share assertion.

Disconfirming Evidence

The thesis implied by this technology map — that advanced packaging is a durable, high-value technology and OSAT/foundry advanced-package capacity will be broadly bought by AI, HPC, mobile, and automotive chip designers — would be materially weakened by the following evidence:

1. UCIe adoption stalls. If only one or two companies adopt UCIe rather than a broad ecosystem, the chiplet-reuse thesis weakens. Evidence would be found in public UCIe membership, actual product pinouts, or absence of UCIe in product specifications [S3].
2. Fine-pitch reliability fails in volume. If micro-bump or hybrid-bond qualification data show unacceptable electromigration or thermal-cycling failure at the pitches described in the worked calculation, then the pitch-density gains are not commercially usable [S2].
3. Advanced-packaging capacity exceeds demand. TSMC’s 20-F risk factors themselves raise the possibility that advanced-packaging capacity expansion may not be fully utilized [S9]. Oversupply would compress foundry packaging premiums and OSAT utilization.
4. Alternative integration paths gain share. If monolithic reticle scaling plus optical I/O or substrate-level improvements reduce the need for silicon interposers, then the 2.5D packaging thesis weakens. Source-wise, that alternative is not established in this note; it would require new primary data.
5. Customer concentration unwinds. Amkor’s 10-K discloses reliance on a limited number of large customers [S8]. Loss of one or two major customers would disprove the assumption of stable OSAT advanced-package demand.
6. The patent cited here is asserted as a moat. This source [S1] does not prove commercial exclusivity or viability; any claim that it alone creates a moat is unsupported until patent claims, assignments, and litigation history are retrieved.