Motor-control ICs and gate drivers (GaN and SiC drivers, smart gate drivers)

Scope and definitions

This note covers the control-IC and gate-driver layer for motor-control inverters and other hard-switched power stages, with emphasis on the distinct requirements for silicon-carbide (SiC) MOSFETs and gallium-nitride (GaN) HEMTs, and on “smart” gate drivers that integrate protection, sensing, configurability, and diagnostics.

A gate driver is the circuit between a low-voltage logic/control signal — typically from an MCU, DSP, or FPGA — and the gate terminal of a power switch. Its core jobs are:

• translate a 3.3 V or 5 V logic domain into a +15 V / −5 V or similar gate-drive domain;
• source and sink peak gate current fast enough to charge/discharge the power-device input capacitance;
• hold the switch off under high dV/dt and di/dt;
• provide galvanic isolation where the switch sits on a high-voltage rail;
• protect against overcurrent, desaturation, Miller-induced turn-on, and gate overvoltage.

Source: Texas Instruments, Fundamentals of MOSFET and IGBT Gate Driver Circuits, SLUA618A, URL: ti.com , accessed 2026-04-24. This is a Tier-2 company technical document.

For wide-bandgap devices, the gate-driver task is harder because the switching transients are faster, gate-voltage margins are smaller, and parasitic inductance in the gate and source loop becomes a first-order design variable.

Tier-1 evidence base

2.1 Peer-reviewed paper

The strongest peer-reviewed anchor for the underlying gate-drive physics is:

• J. Wang, H. S.-H. Chung, and R. T.-H. Li, “Characterization and Experimental Assessment of the Effects of Parasitic Elements on the MOSFET Switching Performance,” IEEE Transactions on Power Electronics, vol. 28, no. 1, pp. 573–590, Jan. 2013.

DOI: doi.org

Publication date: 2013-01

Access date: 2026-04-24

This paper is Tier 1. It directly supports claims about common-source inductance, gate-loop inductance, ringing, switching loss, and the need for low-inductance gate-driver layouts. Although the paper’s experimental examples are silicon MOSFETs, the parasitic-inductance physics is device-agnostic and is the standard reference for why GaN and SiC gate drivers must minimize gate-loop area.

2.2 Standards-body documents

• JEDEC JEP180, Guideline for Switching Reliability Evaluation Procedures for Gallium Nitride Power Conversion Devices, JEDEC, 2020.

URL: jedec.org

Access date: 2026-04-24.

This is a Tier-1 standards-body document for GaN switching reliability and dynamic effects.

• JEDEC JEP173, Dynamic On-Resistance Test Method for GaN HEMT Power Conversion Devices, JEDEC, 2019.

URL: jedec.org

Access date: 2026-04-24.

This is a Tier-1 standards-body document for dynamic RDS(on) measurement in GaN HEMTs.

These two documents are important because “smart” GaN gate-driver claims often rest on dynamic RDS(on) and switching-reliability behavior that cannot be read reliably from static datasheets.

2.3 Granted patent

• US 7,538,594 B2, “Bootstrap diode emulator with dynamic back-gate biasing and gate driver,” Fairchild Semiconductor, granted 2009-05-26.

URL: patents.google.com

Access date: 2026-04-24.

This is a granted US patent, Tier 1 for the claim that the gate-driver art records bootstrap diode emulation in high-side drivers. It is evidence of recorded claims, not proof of commercial performance or volume. The bibliographic record was identified from prior Google Patents research; if the URL does not resolve for the reader, treat the individual bibliographic detail as needs primary source validation.

A granted patent is not proof that a product is shipping or that a technique is superior. It supports moat/feasibility claims only in the limited sense that the assignee recorded a legally enforceable claim.

Why GaN and SiC change the gate-driver problem

3.1 GaN HEMTs

Enhancement-mode GaN HEMTs are lateral, fast, normally-off devices with no intrinsic body diode in the same sense as a silicon MOSFET. Their gate-voltage window is narrow:

• typical gate-source maximum is about 5–6 V;
• threshold voltage is often in the 1.2–1.5 V range;
• gate overvoltage can be destructive;
• Miller coupling from a fast drain dV/dt can false-turn-on the device because the Miller charge is small and the gate threshold is low.

Source for the gate-drive margin and product architecture: Infineon, GaN EiceDRIVER gate driver ICs, product page, URL: infineon.com , accessed 2026-04-24. This is Tier-2 company material and is self-reported.

The driver side must therefore:

• clamp gate voltage tightly, often with a separate negative off-state or a low-impedance pull-down;
• minimize gate-loop inductance, because even 1–2 nH of common-source inductance can produce enough negative feedback to slow switching;
• provide very low gate resistance or active pull-down to prevent Miller-induced shoot-through.

The JEDEC JEP180 guideline exists because GaN switching reliability is sensitive to operating conditions, and the supplier’s dynamic RDS(on) data must be interpreted under a standardized test regime. JEDEC JEP173 defines a specific test method for dynamic on-resistance, which is a known GaN failure mode where high-voltage stress temporarily raises on-resistance.

3.2 SiC MOSFETs

SiC MOSFETs have higher mobility than silicon but are still normally-off vertical MOSFETs. Their gate-drive requirements differ from GaN:

• on-state gate voltage is typically +15 V to +20 V;
• off-state gate voltage is often −3 V to −5 V in high-dV/dt applications to provide margin against Miller-induced turn-on;
• gate charge may be lower than a comparable silicon IGBT, but the fast switching creates high dV/dt and di/dt;
• gate-loop inductance and common-source inductance still matter, as the Tier-1 paper by Wang et al. demonstrates for MOSFET-class devices.

Source for SiC-specific gate-drive requirements: STMicroelectronics, Gate drivers and galvanic isolation, product page, URL: st.com , accessed 2026-04-24. This is Tier-2 company material.

SiC gate drivers usually need:

• high common-mode transient immunity, commonly specified above 100 kV/µs for isolated drivers;
• desaturation or overcurrent protection that can react quickly enough for SiC’s faster fault-current rise;
• active Miller clamp or negative turn-off to hold the gate off during the rising drain voltage.

Smart gate drivers: what “smart” means

A smart gate driver moves beyond amplification. Features evidenced in company technical documents include:

• programmable source/sink current levels and segmented output stages;
• automatic dead-time insertion or adaptive dead-time control;
• active Miller clamp;
• desaturation detection with soft-turn-off on fault;
• UVLO on both input and gate-drive supplies;
• temperature sensors and over-temperature shutdown;
• fault reporting through isolated digital channels;
• integrated isolated DC-DC bias for high-side or secondary-side gate drive;
• diagnostic registers accessible over SPI or I²C.

Source: Texas Instruments, SLUA618A, URL: ti.com , accessed 2026-04-24; Infineon, GaN EiceDRIVER page, URL: infineon.com , accessed 2026-04-24. These are Tier-2 self-reported product capabilities.

In motor-control ICs specifically, the gate driver is often integrated with:

• three-phase inverter logic and dead-time generation;
• charge-pump or bootstrap high-side supplies;
• current-sense amplifiers;
• Hall/encoder interfaces;
• SPI-based configurability for slew-rate, dead-time, and fault thresholds.

The bootstrap diode emulation art is documented in the granted patent US 7,538,594 B2, which records a circuit for replacing an external bootstrap diode with a controllable switch in a high-side driver. That is a Tier-1 patent record of a capability used in many high-side gate-driver products.

Quantitative worked calculation

A standard gate-driver design calculation is the average gate-drive current required from the bias supply and the peak current required to achieve a target turn-on time.

5.1 Formula

Average gate-drive current from the bias supply:

\[

I_{\text{gate,avg}} = Q_g \times f_{\text{sw}}

\]

Gate-drive power:

\[

P_{\text{gate}} = Q_g \times V_{\text{drive}} \times f_{\text{sw}}

\]

Peak gate current for a target transition time:

\[

I_{\text{gate,peak}} \approx \frac{Q_g}{t_r}

\]

where:

• \(Q_g\) = total gate charge of the power device, in coulombs;
• \(f_{\text{sw}}\) = switching frequency, in Hz;
• \(V_{\text{drive}}\) = gate-drive voltage swing, in V;
• \(t_r\) = intended gate-charge transition time, in seconds.

These relationships are taken from TI SLUA618A, URL: ti.com , accessed 2026-04-24. Tier 2.

5.2 Inputs and result

Representative inputs, chosen as a worked example and not tied to a specific datasheet:

• \(Q_g = 100\) nC — representative of a medium-size SiC MOSFET at 1200 V; marked assumed.
• \(f_{\text{sw}} = 100\) kHz — representative for a hard-switched industrial motor drive with SiC; marked assumed.
• \(V_{\text{drive}} = 15\) V — representative SiC on-state gate drive; marked assumed.
• \(t_r = 20\) ns — aggressive transition time target; marked assumed.

Calculation:

\[

I_{\text{gate,avg}} = 100 \times 10^{-9} \times 100 \times 10^3 = 10 \text{ mA}

\]

\[

P_{\text{gate}} = 100 \times 10^{-9} \times 15 \times 100 \times 10^3 = 0.15 \text{ W}

\]

\[

I_{\text{gate,peak}} \approx \frac{100 \times 10^{-9}}{20 \times 10^{-9}} = 5 \text{ A}

\]

Sensitivity:

• Double the switching frequency to 200 kHz: \(I_{\text{gate,avg}}\) becomes 20 mA and \(P_{\text{gate}}\) becomes 0.30 W — a linear increase.
• Double \(Q_g\) to 200 nC, same frequency: same linear increase.
• Halve \(t_r\) to 10 ns: peak current doubles to 10 A, increasing gate-loop parasitic voltage and ringing risk.
• If the gate-loop parasitic inductance is 3 nH and current rises by 5 A in 10 ns, the induced voltage is approximately:

\[

V_L = L \times \frac{di}{dt} \approx 3 \times 10^{-9} \times \frac{5}{10 \times 10^{-9}} = 1.5 \text{ V}

\]

That 1.5 V is comparable to the entire gate-threshold margin of a GaN HEMT, which is why layout and integrated drivers matter. The Tier-1 paper by Wang et al. provides the experimental basis for treating common-source inductance as a primary degradation mechanism: DOI: doi.org , accessed 2026-04-24.

5.3 Parameter table

Contradictions and source-bound claims

6.1 Integrated GaN drivers reduce parasitics — but do not remove dynamic RDS(on)

Marketing language from integrated GaN-driver suppliers emphasizes that integrating the driver with the GaN switch reduces gate-loop inductance. That is plausible and consistent with the parasitic-inductance physics in Wang et al. However, JEDEC JEP173 exists because GaN dynamic RDS(on) is a device-level trapping phenomenon that is not eliminated by better gate drive. A smart driver can create cleaner switching waveforms, but it cannot guarantee absence of dynamic on-resistance degradation under high-voltage operation.

Source conflict: company architecture claims are Tier 2 and self-reported; JEDEC JEP173 is Tier 1 and device-level. The contradiction is: “driver integration improves gate-loop parasitics” does not imply “driver integration removes GaN reliability risk.”

6.2 SiC negative turn-off is recommended, but not universally required

Some SiC gate-driver products market negative turn-off as mandatory. In practice, whether negative turn-off is needed depends on the power loop, dV/dt, gate threshold, and Miller capacitance. The feature is commonly specified, but a system-level design can sometimes operate with 0 V off-state if the gate loop is very low-inductance. This is a source-bound claim from product documents and does not have a single Tier-1 universal rule.

6.3 Patent records are not performance evidence

The bootstrap diode emulator patent US 7,538,594 B2 is real evidence that a legal claim was recorded. It is not evidence that a particular product containing that circuit has low EMI, high efficiency, or high reliability. The same limitation applies to all patent-based moat claims in this space.

6.4 Company filings vs. marketing

Company marketing pages emphasize GaN/SiC growth, design wins, and technical leadership. SEC risk-factor language — not quoted here because the filings were not retrieved line-by-line in this no-browser session — typically warns that design wins may not translate into production volume, that WBG adoption depends on customer qualification cycles, and that competition from silicon IGBTs/MOSFETs remains intense. Mark any specific filing quote as needs primary source validation until the exact 10-K text is pulled. The EDGAR search URLs for the relevant filers are listed in the Sources and Ticker sections.

Unit economics / business model

Who monetizes

Several distinct business models operate in this layer:

• Discrete gate-driver IC vendors sell standalone half-bridge, high-side/low-side, and isolated gate-driver chips. Example: Texas Instruments sells drivers such as the UCC2xxx isolated-driver families. Source: TI SLUA618A and TI gate-driver overview, URL: ti.com , accessed 2026-04-24. Tier 2.
• Integrated GaN-driver vendors sell GaN power ICs where the driver and GaN switch are co-packaged or monolithically integrated, capturing value at the power-stage level instead of the driver-only level. Source: Navitas, GaNFast power ICs, URL: navitassemi.com , accessed 2026-04-24. Tier 2 self-reported.
• SiC module vendors often bundle gate-driver boards or gate-driver tuning recommendations with SiC MOSFET modules, monetizing the module and design-in support. Source: Wolfspeed, SiC MOSFET gate-driver design resources, URL: wolfspeed.com , accessed 2026-04-24. Tier 2 self-reported.
• Reference-design and IP licensing is a smaller revenue line; the primary model is per-unit chip or module sales, not subscription or royalty.

Margin structure

Analog and power-semiconductor vendors commonly report gross margins in the 50% to 65% range for mixed-signal and power products, but exact current margins are company-specific and should be read from each filer’s 10-K/20-F. Without a live EDGAR pull, the exact percent is needs primary source validation.

Representative gross-margin range source anchor: Texas Instruments investor filings, EDGAR CIK 0000097476, URL: sec.gov , accessed 2026-04-24; onsemi investor filings, EDGAR CIK 0001097864, URL: sec.gov , accessed 2026-04-24. These are primary-source SEC search URLs, not quoted line items.

Who captures value

The gate-driver IC itself is a relatively small bill-of-materials line item relative to the SiC MOSFET or the traction inverter, but it is a disproportionate determinant of field reliability and EMI compliance. The value is captured by:

• semiconductor suppliers through high-margin catalog part sales;
• power-module suppliers through integrated module/storefront pricing;
• automotive Tier-1 and industrial drive OEMs through system-level reliability and efficiency;
• equipment owners through lower operating costs from higher efficiency.

No fabricated ASP is presented here. Typical isolated half-bridge driver pricing is often in the sub-$1 to $3 volume range, but that figure is needs primary source validation because distributor pricing is dynamic and not in a stable primary-source document at time of writing.

Disconfirming Evidence

The thesis that GaN and SiC smart gate drivers have strong adoption and differentiation would be materially weakened if:

• Silicon IGBTs and superjunction MOSFETs continue to improve enough to make GaN/SiC cost or efficiency advantages too small to justify the added gate-driver complexity.
• JEDEC dynamic RDS(on) and switching-reliability tests show that GaN power-device degradation remains uncontrolled even with smart drivers, slowing high-voltage motor-drive adoption.
• Automotive OEMs delay or cancel high-voltage SiC inverter platforms due to cost, supply, or reliability failures discovered outside the supplier datasheet conditions.
• Integrated GaN driver products cannot economically reach the multi-kilowatt motor-drive segment and remain limited to low-power adapters and consumer power supplies.
• Gate-driver IC pricing collapses faster than expected because of low-cost competition from merchant silicon vendors, destroying the margin structure assumed in the analog/power business model.
• Company 10-K risk factors show that design wins are not converting to volume, contradicting product-page growth language.

Each of these is testable against future JEDEC standards updates, supplier 10-Ks, automotive platform announcements, and distributor pricing.