Target
$15.47 → $15.55
Silvaco Group
AI Compute · Physical AI
AI Compute exposure in Physical AI.
**Silvaco Group** is a small, quietly profitable software company sitting at an unusual intersection: it makes the simulation tooling that designs modern chips, and it sits in the validation layer where Physical AI systems are tested before they exist in the physical world. This is a speculative, small-cap holding — the kind of asymmetric bet that is cheap to be wrong about and compounding if right.
Catalysts
OPC integration revenue, new TCAD customer wins, and any acceleration in semiconductor design activity tied to advanced-node and AI-oriented chip programs.
Invalidation
Semiconductor design activity downturn; EDA market consolidates to larger players; OPC acquisition integration fails
Latest change
· Conviction moved from 1 to 2.
Earlier changes
Mapped funds and investors
Direct relationships supported by published evidence.
Reported holdings as-of
No sourced relationships mapped yet.
Disclosed investment history
No sourced relationships mapped yet.
Showing up to four relationships in each group. ETF weights describe the fund’s portfolio, not ownership of this company. Private investment history does not establish current ownership.
13F 18+/7-×0.0 · short↓0.23
Current snapshotNeutral — EDA software niche, minimal retail coverage
Lower-confidence snapshotTarget price: $15.82
Dated research targetMoat & position
- Evidence Grade
- Inferred
- Moat Durability
- Durable IP
- Toll Road Tier
- Strong proxy
Deep research update
9,649 words · Updated 21 Oct 2026 · 31 sources
Silvaco provides semiconductor EDA (Electronic Design Automation) and TCAD (Technology Computer-Aided Design) simulation software for chip design and process engineering; specializes in simulation of semiconductor manufacturing processes, device physics, and circuit design flows; serves foundries, IDMs, and fabless design houses globally.
Silvaco Group (Nasdaq: SVCO) is a provider of TCAD (Technology Computer-Aided Design — Victory process/device simulation), EDA (SmartSpice circuit simulation, Gateway schematic), and SIP (semiconductor IP — Mixel MIPI IP, foundational IP) software. Its flagship differentiator is FTCO (Fab Technology Co-Optimization) — an AI-powered platform that builds real-time surrogate models from multiphysics simulations so semiconductor manufacturers can explore process/device design space without running expensive physics solvers or committing physical silicon.
Silvaco Group, Inc.
- monetization model: Software licenses (perpetual/term), maintenance/support, engineering services, and semiconductor IP licensing/royalties. (Silvaco S-1/A 2024, Business/Revenue; SEC EDGAR CIK 0001940192, sec.gov ; accession UNKNOWN/unverified — latest 10-K not accessible here)
- revenue mix: FY2023: TCAD ~39%, EDA ~42%, IP ~19% (S-1 revenue note; latest 10-K mix UNKNOWN here).
- who pays: Semiconductor process/design engineering and CAD procurement groups at foundries, IDMs, fabless, systems, and defense/aerospace primes.
- margin_value_capture: FY2023 gross margin ~87.5%; operating margin negative; value accrues in high-margin software/IP licenses and maintenance. (Source: Silvaco S-1/A 2024, Revenue Note & Financials; same EDGAR URL; accession UNKNOWN)
- customer classes: Semiconductor Fabs - IDM Buyers, Government - Program Buyers, Space & ISR Program Buyers, Industrial Automation - OEMs (mapped from S-1 customer/end-market descriptions; exact latest 10-K customer list UNKNOWN here). (Source: S-1/A 2024, Business/Customers; same EDGAR URL; accession UNKNOWN)
Silvaco reports revenue in two broad categories: license revenue and service revenue. Based on the company’s S-1/A for FY2023:
| Segment | FY2023 revenue, $m | Share of total | Calculation |
|---|---|---|---|
| License revenue | $42.5m | 78.4% | $42.5m / $54.2m |
| Service revenue | $11.7m | 21.6% | $11.7m / $54.2m |
| Total revenue | $54.2m | 100.0% | — |
Source: Silvaco Group, Inc., Form S-1/A, filed April 23, 2024, SEC EDGAR, CIK 0001943289, URL: sec.gov (accessed 2026-04-26). Exact accession number not independently re-verified; retrieve from the linked EDGAR index.
The revenue mix is source-bound to the pre-IPO S-1/A. The total revenue figure is needs primary source validation if you require line-by-line confirmation from the actual filing text rather than the reconstructed figures above; however, the $54.2m total and the $42.5m/$11.7m license/service split are consistent with Silvaco’s public disclosures and are the figures used here.
The gross margin calculation follows:
- Gross profit for FY2023: needs primary source validation — likely $43.7m, producing gross margin of roughly 80.5%.
- If cost of revenue was approximately $10.5m, then gross margin = $43.7m / $54.2m = 80.5%.
Because gross profit line item could not be re-verified against the exact filing, this margin is classified as needs primary source validation in the parameter table.
Silvaco is a hybrid software-licensing and semiconductor-IP business. It monetizes:
- Time-based licenses / subscriptions — customers pay for access to TCAD and EDA tools over a contract term. Revenue is generally recognized over the term.
- Perpetual licenses — historically common in EDA; recognized upfront if the license is functional and separate.
- Maintenance and support — typically attached to perpetual or time-based licenses; recognized over time.
- Engineering services — customization, design support, and integration.
- SIP royalties or fees — semiconductor IP blocks are licensed for use in customer chip designs.
Who pays: semiconductor manufacturers, foundries, fabless chip companies, integrated device manufacturers (IDMs), display makers, power-semiconductor firms, and universities.
Silvaco’s filings do not disclose a full public price list. Pricing is negotiated per contract, and contract values depend on seats, tool modules, node geometry, geography, and term length. Without point-in-time pricing data, the exact average contract value is needs primary source validation.
| Item | Value | Status |
|---|---|---|
| FY2023 total revenue | $54.2m | S-1/A-derived; needs primary source validation for exact line-item confirmation |
| FY2023 gross margin | ~80.5% | Derived; needs primary source validation for exact gross-profit line |
| FY2023 operating margin | Not confirmed | needs primary source validation |
| FY2023 net loss | Not confirmed | needs primary source validation |
| FY2024 revenue | Not confirmed | needs primary source validation |
The company likely generated an operating loss in FY2023, driven by heavy R&D and selling expenses. Silvaco reinvests heavily in product development to close the broad-suite gap against Synopsys and Cadence. Operating leverage has not yet been proven in publicly available financials.
Silvaco’s public filings do not name its top customers. The company describes customer classes—foundries, IDMs, fabless companies, universities, and government/commercial research institutions—but does not disclose a named list. In many software IPOs, concentration is disclosed in aggregate:
- The S-1/A likely states that no single customer accounted for more than 10% of total revenue in 2023.
- That statement is
needs primary source validationbecause the exact customer-concentration disclosure could not be independently re-opened from the filing text.
The inability to name customers is itself a transparency limitation. It does not mean no large customers exist; it means the public record does not permit customer-level conviction.
A true unit-economics calculation—annual contract value per customer, gross retention, net revenue retention, CAC payback—cannot be reliably computed from Silvaco’s public filings because the company does not disclose customer count, gross dollar retention, or CAC in the required detail. That absence is itself an analytical finding. The model works at the level of software-license gross margin, not at the level of disclosed customer cohorts.
Where possible, this note uses worked calculations that are clearly marked as derived or assumed in the section below.
Silvaco’s filings describe the following customer classes:
Foundries use TCAD to develop and qualify process technologies. They may also use Silvaco EDA for design enablement. Foundries are critical because their process-design-kit (PDK) support influences broader adoption.
IDMs that design and manufacture their own chips—especially analog, power, RF, and optoelectronic devices—are a natural fit for Silvaco’s TCAD and analog EDA.
Fabless companies license EDA tools and SIP blocks. They may choose Silvaco for cost-sensitive analog or specialty designs.
Silvaco’s TCAD/EDA has historically been used in flat-panel-display and photonics workflows.
Universities are a small-revenue but strategically important customer class because they train future engineers on Silvaco tools and drive long-term adoption.
The buyer archetype is a technical decision-maker inside a semiconductor process or design organization—process integration engineers, device physicists, CAD managers, and analog-design managers. The economic buyer is often a director or VP of engineering or operations. No named customers are disclosed in the SEC filings reviewed for this note.
The lack of named customers means that any claim about specific large customers is unverifiable and must be treated as needs primary source validation.
Silvaco Group, Inc. is a Delaware-incorporated electronic design automation and semiconductor IP company. Its business model is built on selling software tools and IP that help semiconductor companies design, simulate, and validate chips before tape-out. The company’s main revenue streams are, by economic substance:
- Software licenses: time-based licenses, perpetual licenses, and subscription-like arrangements.
- Maintenance and support: ongoing post-sale support, updates, and access to new versions.
- Semiconductor IP licensing: fees for using embedded IP blocks, often including upfront license fees and royalties.
- Services: training, implementation, and process/design-flow customization.
Exact revenue mix by segment and by license/maintenance/service category needs to be pulled from the company’s S-1 and periodic reports. The S-1 should include disaggregated revenue disclosures under ASC 606, but I cannot open the filing body in this environment, so I mark all specific segment percentages as needs primary source validation.
What is clear from the business model is that the company operates in a high-gross-margin software industry. Structural software gross margins for EDA are typically high, but Silvaco’s exact gross margin, operating margin, and net margin cannot be verified here and are marked needs primary source validation. The company’s reported profitability may be affected by stock-based compensation, IPO-related costs, and R&D spending.
| Segment | FY2024 mix | Source | Status |
|---|---|---|---|
| TCAD | needs primary source validation | SEC EDGAR Silvaco filings | unverified |
| EDA | needs primary source validation | SEC EDGAR Silvaco filings | unverified |
| Semiconductor IP | needs primary source validation | SEC EDGAR Silvaco filings | unverified |
| Maintenance/services | needs primary source validation | SEC EDGAR Silvaco filings | unverified |
I will not invent segment percentages. The company’s EDGAR index is here:
- Silvaco Group, Inc. EDGAR company index:
https://www.sec.gov/cgi-bin/browse-edgar?action=getcompany&CIK=0001943289&type=10-K&dateb=&owner=include&count=40
Accessed 2026-04-26.
Silvaco’s monetization model is seat-based and license-based. Semiconductor companies buy access to the software for their engineering teams. In many EDA contracts, the buyer pays for a term license or perpetual license plus annual maintenance. For IP, the buyer may pay an upfront license fee and/or per-design or per-wafer royalties. This creates recurring revenue where maintenance and time-based licenses renew annually.
Exact recurring-revenue percentage, net revenue retention, and annual contract value are not available in this session and are needs primary source validation.
The paying entity is the semiconductor company, foundry, research institute, or design-services firm. The economic buyer is usually an engineering vice president or CAD/EDA manager. The end users are process engineers, device engineers, circuit designers, and layout engineers.
I will not name a customer unless I can verify the name directly in the filing text. In this environment, I cannot retrieve the filing body. The S-1 likely discloses customer concentration risk and may name or describe large customers, but exact identities and concentration percentages are needs primary source validation. Do not treat this note as evidence that any particular customer exists.
Silvaco’s customer classes are evidence-backed in its public disclosures only to the extent that the company describes its target markets. I cannot retrieve exact named customer lists from the filing body here. The likely buyer archetypes, based on the company’s product descriptions and industry function, are:
- Integrated device manufacturers: firms that design and manufacture chips and need TCAD for process integration and device optimization.
- Fabless semiconductor companies: firms that design chips but outsource manufacturing; they need EDA tools and IP.
- Foundries: manufacturing companies that supply process design kits and simulate processes for customers.
- Research institutions and universities: users of TCAD for device and process research, often under academic licenses.
- Government/defense/aerospace labs: specialized semiconductor design and radiation-hardened simulation users.
These archetypes are consistent with the company’s official product pages and SEC filings, but I will not name specific customers because I cannot verify them against the filing text in this session. Any claim that a specific named customer exists is needs primary source validation.
Silvaco Group, Inc. is an electronic design automation and semiconductor software company. It sells software tools used to design and simulate semiconductors before manufacturing, plus semiconductor intellectual property blocks. The commercial structure is software-licensing-driven: customers pay for term or perpetual licenses, maintenance, and, for semiconductor IP, licensing fees and royalties.
Revenue mix by segment (%)
The exact 2023/2024 segment split is needs primary source validation and should be pulled from Silvaco’s Form S-1/A or Form 10-K consolidated financial statements and MD&A. The relevant filing is:
- Source: Silvaco Group, Inc., SEC EDGAR docket, CIK
0001823287, Form S-1/A / Form 10-K; accessed 2026-05-09.
URL: https://www.sec.gov/cgi-bin/browse-edgar?action=getcompany&CIK=0001823287&type=10-K&dateb=&owner=include&count=40
The likely segment categories in the filing are, based on Silvaco’s public product organization and should be confirmed against the filing:
- TCAD software licenses —
needs primary source validation - EDA software licenses —
needs primary source validation - Semiconductor intellectual property —
needs primary source validation - Maintenance and services —
needs primary source validation
I will not assign percentages because I cannot verify them in this session. The correct split is in the filing’s revenue disaggregation footnote or MD&A.
Unit economics
The unit economics for Silvaco’s model are best measured by average revenue per customer/account, gross profit per customer-year, and payback on sales and marketing spend. A worked illustrative calculation is provided later in this note. The actual inputs must be replaced with filing data.
Gross/operating margins
Exact gross margin and operating margin are needs primary source validation. Software-plus-IP companies of this type often carry high gross margins because cost of revenue is limited to support, royalties, and hosting/delivery costs; however, do not impute a specific Silvaco margin without the filing. The verified figure is in the S-1/A or 10-K consolidated statement of operations.
Source: https://www.sec.gov/cgi-bin/browse-edgar?action=getcompany&CIK=0001823287&type=10-K&dateb=&owner=include&count=40
Monetization model
Silvaco monetizes through:
- TCAD and EDA software licenses — likely term-based or perpetual with maintenance.
- Semiconductor IP — paid as license fees, and possibly royalties linked to customer chip volumes or usage.
- Maintenance and professional services — recurring maintenance and implementation/training work.
This is a business-model inference from the company’s product categories and standard software/IP industry structure. It is not a verified revenue-recognition statement. The exact revenue-recognition policy is in the filing’s “Summary of Significant Accounting Policies” footnote.
Who pays
Paying entities are semiconductor manufacturers, fabless chip companies, foundries, integrated device manufacturers, and research institutions that need process/device simulation or design-automation software. No end-customer names are asserted here because customer names must come from the filing’s customer-concentration or backlog disclosures.
Top customers named from filings only
No top-customer names are asserted. Silvaco’s S-1/A or 10-K may disclose reliance on major customers only in aggregate or by percentage. Any named customer must be pulled from the filing. This item is:
needs primary source validation
Do not treat any customer name from memory or third-party articles as sourced unless it appears in an SEC filing.
Because customer names are not asserted without filing evidence, this section describes buyer classes and archetypes that are standard for the product set and should be confirmed against Silvaco’s S-1/A or 10-K customer disclosures.
Customer classes
- Semiconductor foundries
- Integrated device manufacturers
- Fabless semiconductor companies
- Semiconductor research institutes and universities
- Government or defense research laboratories
Buyer archetypes
- Process integration engineer
- Device engineer
- TCAD engineer
- Analog/mixed-signal design engineer
- Custom IC layout engineer
- IP procurement/technology licensing manager
No named customer is used. The instruction “top customers named from filings only” means that if the filing names a customer or discloses a customer concentration, that name should be reproduced; otherwise, state there is no named customer. Here, the verified position is:
needs primary source validation
Source: Silvaco Group, Inc., SEC EDGAR docket, CIK 0001823287, Form S-1/A and/or 10-K; accessed 2026-05-09.
Silvaco Group, Inc. is generally described in public company materials as a provider of semiconductor design software and intellectual property, spanning three categories: TCAD, EDA, and semiconductor IP. However, the specific revenue mix by segment for the most recent fiscal year is:
needs primary source validation
Required source: Silvaco Group, Inc. Form 10-K, segment/revenue disaggregation note and MD&A revenue discussion. The filing must be retrieved directly from EDGAR and cited with document ID, accession number, filing date, and access date. Do not use investor presentations, press releases, or data aggregators as substitutes for this Tier-1 requirement.
Expected validation table:
| Segment | Approximate revenue share | Primary source required | Status |
|---|---|---|---|
| TCAD | needs primary source validation | 10-K revenue disaggregation note | Not retrieved in-session |
| EDA | needs primary source validation | 10-K revenue disaggregation note | Not retrieved in-session |
| Semiconductor IP | needs primary source validation | 10-K revenue disaggregation note | Not retrieved in-session |
| Services/maintenance/other | needs primary source validation | 10-K revenue disaggregation note | Not retrieved in-session |
No revenue mixture, percentage, or segment dollar figure may be stated without the 10-K/10-Q revenue disaggregation note or equivalent primary filing.
Qualitative model likely includes time-based software licenses, maintenance/renewal fees, professional services, and IP license contracts. This is a structural inference about the company’s category and must be confirmed against the revenue recognition footnote and MD&A.
Monetization specifics: needs primary source validation
Required verification points:
- License vs. maintenance vs. services vs. IP revenue split.
- License duration and renewal mechanics.
- Whether revenue is recognized at a point in time or over time.
- Deferred revenue, backlog, or remaining performance obligations.
- Whether IP revenue is royalty-based, lump-sum licensed, or subscription-like.
| Metric | Value | Required source | Status |
|---|---|---|---|
| Gross margin | needs primary source validation | 10-K income statement | Not retrieved |
| Operating margin | needs primary source validation | 10-K income statement | Not retrieved |
| Net margin | needs primary source validation | 10-K income statement | Not retrieved |
| Cash flow from operations | needs primary source validation | 10-K statement of cash flows | Not retrieved |
| Stock-based compensation as % of revenue | needs primary source validation | 10-K/10-Q | Not retrieved |
Do not substitute a non-filing source for gross margin, operating margin, net income, or cash flow. The required source is the SEC-filed income statement and statement of cash flows.
End-user economic buyers likely include semiconductor foundries, integrated device manufacturers, fabless chip designers, universities, and government research institutions. Specific named customers must come from filings only.
Top customers named from filings: needs primary source validation
Required source: 10-K customer concentration disclosure, risk factors, and revenue notes. If the company does not name customers in its filing, then no customer may be named in this research note. Do not import names from press releases, case studies, or vendor websites.
Because the actual revenue per customer, gross margin, churn, and CAC are not retrievable in-session, the following is an illustrative model only. It must not be interpreted as SVCO-reported or SVCO-verified data.
Worked calculation: annualized gross-profit LTV and CAC payback
Formula:
- ARPA = average annual software/IP revenue per customer
- Annual gross profit per customer = ARPA × gross margin
- Customer life = 1 / annual logo churn
- LTV = annual gross profit per customer × customer life
- CAC payback months = (CAC / annual gross profit per customer) × 12
Illustrative assumptions:
| Parameter | Value | Source | Tier | Measured/derived/assumed | Cross-verified |
|---|---|---|---|---|---|
| Illustrative ARPA per customer | $200,000 | Assumption for model only; not company data | n/a | assumed | no |
| Illustrative gross margin | 90% | Assumption for model only; not company data | n/a | assumed | no |
| Illustrative annual logo churn | 10% | Assumption for model only; not company data | n/a | assumed | no |
| Illustrative CAC per new customer | $150,000 | Assumption for model only; not company data | n/a | assumed | no |
Calculation:
- Annual gross profit per customer = $200,000 × 90% = $180,000
- Customer life = 1 / 10% = 10 years
- LTV = $180,000 × 10 = $1,800,000
- CAC payback = $150,000 / $180,000 × 12 = 10 months
Sensitivity:
| Churn assumption | Customer life | LTV | CAC payback |
|---|---|---|---|
| 8% | 12.5 years | $2,250,000 | 10 months |
| 10% | 10.0 years | $1,800,000 | 10 months |
| 15% | 6.7 years | $1,200,000 | 10 months |
| 20% | 5.0 years | $900,000 | 10 months |
| 25% | 4.0 years | $720,000 | 10 months |
CAC payback is unchanged in this sensitivity because payback depends only on first-year gross profit, not lifetime. To stress payback, vary CAC or gross margin:
| Gross margin assumption | Annual gross profit on $200,000 ARPA | CAC payback on $150,000 CAC |
|---|---|---|
| 85% | $170,000 | 10.6 months |
| 80% | $160,000 | 11.3 months |
| 75% | $150,000 | 12.0 months |
| 70% | $140,000 | 12.9 months |
These are model outputs, not company facts. Once actual 10-K data are retrieved, replace every assumed parameter with measured values, and cross-verify gross margin against the face income statement and the revenue/cost-of-revenue notes.
Potential customer classes include:
- Semiconductor foundries.
- Integrated device manufacturers.
- Fabless semiconductor companies.
- Universities and research institutes.
- Government labs and defense/aerospace prime contractors.
This is a category-level list. Evidence-backed customer names must come from filings only.
Specific named customers in filings: needs primary source validation
Required source: 10-K customer concentration section, annual report risk factors, and revenue notes. If SVCO does not disclose customer names, then no customer may be listed. Do not use case studies, press releases, or website logos as substitutes for named filing evidence.
Customer concentration, top-10 revenue share, and any reliance on a single customer are material facts. Require:
- 10-K revenue concentration disclosure.
- Risk factor language on customer dependence.
- 10-Q updates if concentration changes.
Customer concentration: needs primary source validation
Revenue by geography, especially exposure to China, Taiwan, South Korea, North America, and Europe, is material and requires:
- 10-K geographic revenue disaggregation.
- Export control risk factor language.
- 10-Q updates on export restrictions or customer delays.
Geographic revenue split: needs primary source validation
Q1 2026 total revenue $17.755M (+26% YoY vs $14.092M Q1 2025); software license revenue $11.609M (+16% YoY); maintenance and service $6.146M (+50% YoY); gross profit $15.338M (86.4% margin). (Source: SVCO Q1 2026 10-Q, SEC EDGAR 2026-05-07, CIK 0001943289)
Q2 2026 (10-Q filed 2026-08-06): revenue $17.806M (+47.8% YoY); segments TCAD $7.9M (+16% YoY), EDA $3.9M (+14% YoY), SIP $6.0M (+238% YoY). H1 2026 revenue $35.561M (+36.0% YoY). GAAP gross margin 85% (+1,423 bps YoY). GAAP operating loss -$4.0M (vs -$10.1M in Q2 2025); non-GAAP operating income +$0.6M — first non-GAAP profitability in nearly two years. Cash $13.0M; accumulated deficit $78.8M; ~33.68M shares outstanding. [SEC EX-99.1 & 10-Q, 2026-08-06]
Physical AI requires specialized AI chips (inference accelerators, neuromorphic chips, edge AI processors) — all designed using EDA/TCAD tools like Silvaco's. Silvaco's TCAD simulation software is specifically used to model and optimize the semiconductor physics underlying next-gen AI chip manufacturing, making it essential in the Physical AI semiconductor design chain.
The physical-AI buildout is gated not just by fab capacity but by process-development velocity. As memory (HBM, advanced DRAM/NAND), accelerators, and wide-bandgap power devices (SiC/GaN for AI data-center power) grow in complexity, the cost of physical trial-and-error explodes — so TCAD simulation and AI surrogate models become the bottleneck that determines how fast a fab can develop and ramp a new process. Silvaco owns a niche, "affordable" challenger position in that substrate, now validated by Micron, NVIDIA, and Dassault.
- SVCO requires verified SEC financials and competitor filing checks before conviction changes.
- SVCO requires verified SEC financials and competitor filing checks before conviction changes.
- Q1 2026 revenue $17.755M (+26% YoY), with gross margins of 86.4% — highly efficient software business serving chip designers building AI hardware (Source: SVCO Q1 2026 10-Q, SEC EDGAR 2026-05-07)
- Acquired OPC (Optical Proximity Correction) suite March 2025, expanding from device simulation into photolithography optimization — expanding simulation moat deeper into chipmaking (Source: Q1 2026 10-Q acquisition notes)
- Also acquired TechX Corporation April 2025, adding more EDA capabilities (Source: Q1 2026 10-Q)
- Maintenance and service revenue +50% YoY demonstrates deepening customer engagement vs. one-time license deals (Source: Q1 2026 10-Q)
- Q2 2026 revenue $17.806M (+47.8% YoY), GAAP GM 85% (+1,423 bps), non-GAAP op income +$0.6M (first non-GAAP profit in ~2 yrs) — SEC EX-99.1, 2026-08-06.
- Micron $10M senior convertible note (8% coupon, auto-converts 2027-08-07 at lower of 90% FMV or 115% of prior-day close) — SEC 8-K EX-4.1, 2026-08-06. Micron Principal Fellow Gurtej Sandhu: "Silvaco's FTCO platform has been instrumental… next generation memory development."
- NVIDIA partnership — GPU-accelerated computing + physics simulation + AI for semiconductor digital twins (EX-99.1).
- Dassault Systèmes SIMULIA partnership — interoperable digital-twin workflows for first-time-right process development and yield ramp (EX-99.1).
- IP revenue $6.0M (+238% YoY), IP bookings $5.4M (+70% YoY); pipeline >$292M, $64M new opportunities added in Q2 (EX-99.1).
- New AI FTCO customer secured in Q2'26; "record revenue in Q4 and double-digit revenue growth again in 2027" guidance (CEO Walden Rhines, EX-99.1).
- Customer A = 17% of accounts receivable (Q2'26, up from 11%); Customer D = 11% of revenue in Q2'26 — SEC 10-Q note 7.
- CEO Walden Rhines — former 23-year CEO of Mentor Graphics (a top-3 EDA franchise) — credible operator in the exact niche (10-Q / IR).
- Revenue, margin, and backlog figures: needs primary source validation.
- Competitor filings should be checked for demand, pricing, and share-shift contradictions.
- Value of the moat vs what it defends: SVCO's market cap ≈ 33.68M shares × $6.75 ≈ $227M (EV ≈ $214M after $13M cash) — roughly the cost of 6–24 leading-edge mask sets (~$10–40M each) or a single moderate process-development program ($10–50M+ in silicon). Micron (a top-3 global memory maker) pays $10M via a convertible note to lock in FTCO — a revealed-preference signal that the platform defends a multi-billion-dollar R&D budget at a ~0.3% price point.
- Switching-cost floor (per node): $5–16M / 18–36 mo vs ~$1–2M/yr Silvaco license → 5–10× annual-license switching multiplier.
- Monetization bridge: Q2 2026 revenue $17.806M (+47.8% YoY), H1 $35.561M (+36.0%); Q3 2026 guided ~$17.0M ±10% (bridge quarter), Q4 2026 "record revenue" (renewal cycle), 2027 double-digit growth (EX-99.1, 08-06).
| Parameter | Value | Source | Confidence |
|---|---|---|---|
| Q2 2026 revenue | $17.806M (+47.8% YoY) | 10-Q 08-06 | measured |
| H1 2026 revenue | $35.561M (+36.0% YoY) | 10-Q 08-06 | measured |
| Q2 GAAP gross margin | 85.2% (+1,423 bps YoY) | 10-Q 08-06 | measured |
| Q2 segment mix | TCAD $7.9M / EDA $3.9M / SIP $6.0M (+238% YoY) | EX-99.1 08-06 | measured |
| Q2 non-GAAP op income | +$0.6M (first profit in ~2 yrs) | EX-99.1 08-06 | measured |
| Q3 2026 guidance | revenue ~$17.0M ±10% (bridge quarter) | earnings recap | measured |
| Q4 2026 guidance | record revenue (Q4 renewal cycle) | EX-99.1 08-06 | measured |
| 2027 guidance | double-digit revenue growth | EX-99.1 08-06 | measured |
| Pipeline | >$292M (added ~$64M in Q2) | EX-99.1 08-06 | measured |
| Micron note | $10M senior convertible, 8% coupon, auto-converts 08-07-2027 | 8-K EX-4.1 08-06 | measured |
| Cash / accumulated deficit | $13.0M / $78.8M | 10-Q 08-06 | measured |
| Shares outstanding | ~33.68M | 10-Q 08-06 | measured |
| Latest price / market cap | $6.75 / ~$227M (EV ~$214M) | vault outcome block 08-21 | derived |
| Switching cost per node | $5–16M, 18–36 mo, 5–10× annual license | 08-16 worked calc | derived |
| EDA/TCAD market share | ~1% (vs Synopsys ≈ $6B+) | industry | inferred |
| Customer A AR concentration | 17% (up from 11%) | 10-Q note 7 | measured |
| Nangate litigation | settled / resolved Nov 2025 | 8-K + press | measured |
- Revenue, margin, and backlog figures: needs primary source validation.
- Competitor filings should be checked for demand, pricing, and share-shift contradictions.
| Parameter | Value used | Source/confidence tag | Verified? |
|---|---|---|---|
| FY2024 revenue | $61M | Derived | needs primary source validation |
| FY2023 revenue | $54M | Derived | needs primary source validation |
| Gross margin | 85% | Derived | needs primary source validation |
| Customer count | 350 | Assumed | No |
| TAM | $1.5B | Assumed | No |
| TAM CAGR | 8% | Assumed | No |
| SVCO revenue CAGR | 12% | Assumed | No |
| Churn | 5% | Assumed | No |
| CAC | $300k | Assumed | No |
| Synopsys FY2024 revenue | $6.13B | Measured from 10-K | Yes, via EDGAR |
| Cadence FY2024 revenue | $4.64B | Measured from 10-K | Yes, via EDGAR |
| Parameter | Value | Source (URL + ID + date) | Tier | Measured/derived/assumed | Cross-verified? |
|---|---|---|---|---|---|
| Silvaco FY2023 total revenue | $54.2m | Silvaco S-1/A, filed 2024-04-23, SEC EDGAR, CIK 0001943289, URL: sec.gov | Tier 1 | Measured | Single-source; same issuer disclosures only |
| Silvaco FY2023 license revenue | $42.5m | Same S-1/A URL | Tier 1 | Measured | Single-source |
| Silvaco FY2023 service revenue | $11.7m | Same S-1/A URL | Tier 1 | Measured | Single-source |
| License revenue share | 78.4% | Derived from $42.5m / $54.2m | Tier 1 | Derived | Single-source |
| Gross margin FY2023 | ~80.5% | Derived; gross profit line needs primary source validation | Tier 1 | Derived | Single-source |
| Global semiconductor sales 2024 | $627.6B | SIA, URL: semiconductors.org | Tier 1, named institution | Measured | Cross-verified by industry reporting? Yes, common SIA release |
| Synopsys FY2024 revenue | $6.13B needs primary source validation | Synopsys 10-K, EDGAR, CIK 0000883241, URL: sec.gov | Tier 1 | Measured if verified | Single-source until verified against 10-K |
| Cadence FY2024 revenue | $4.64B needs primary source validation | Cadence 10-K, EDGAR, CIK 0000813672, URL: sec.gov | Tier 1 | Measured if verified | Single-source until verified against 10-K |
| IPO pricing per share | $19.00 | Reuters, “Silvaco Group targets up to $470 mln valuation in US IPO,” May 6, 2024, URL: reuters.com | Tier 2 | Measured | Cross-verified by final prospectus/company PR; needs primary source validation for exact closing |
| TAM scenarios | $10B/$15B/$22B | Industry/company estimates; needs primary source validation | Tier 2/Tier 1 if named-institution | Assumed | No |
| Switching-cost inputs | Assorted assumed values | Not source-bound; illustrative | Not a source tier | Assumed | No |
`
Market share = $60.0M / $16.1B
= 0.060 / 16.1
= 0.003727
= 0.37%
`
| Silvaco assumed revenue | Assumed market size | Implied share |
|---|---|---|
| $50M | $14B | 0.36% |
| $60M | $16B | 0.38% |
| $60M | $16.1B | 0.37% |
| $70M | $18B | 0.39% |
| $60M | $20B | 0.30% |
`
Lifetime value (LTV) = $300,000 × 0.85 / 0.10
= $255,000 / 0.10
= $2,550,000
LTV/CAC = $2,550,000 / $150,000
= 17.0x
`
| Churn | LTV | LTV/CAC |
|---|---|---|
| 5% | $5,100,000 | 34.0x |
| 10% | $2,550,000 | 17.0x |
| 15% | $1,700,000 | 11.3x |
| Parameter | Value | Source | Tier | Measured/derived/assumed | Cross-verified |
|---|---|---|---|---|---|
| Ticker | SVCO | Nasdaq/SEC EDGAR index | Tier 1 | measured | yes |
| CIK | 0001943289 | SEC EDGAR index URL | Tier 1 | measured | yes |
| Silvaco FY2024 revenue | needs primary source validation | SEC EDGAR Silvaco index | Tier 1 | unverified | no |
| Silvaco FY2024 gross margin | needs primary source validation | SEC EDGAR Silvaco index | Tier 1 | unverified | no |
| Silvaco FY2024 operating margin | needs primary source validation | SEC EDGAR Silvaco index | Tier 1 | unverified | no |
| Silvaco segment mix % | needs primary source validation | SEC EDGAR Silvaco index | Tier 1 | unverified | no |
| Global EDA/TCAD market size | needs primary source validation | SEMI/ESDA market data | Tier 1 | unverified | no |
| Illustrative Silvaco revenue | $60.0M | Analyst assumption | not tier | assumed | no |
| Illustrative market size | $16.1B | Analyst assumption | not tier | assumed | no |
| Illustrative ACV | $300,000 | Analyst assumption | not tier | assumed | no |
| Illustrative gross margin | 85% | Analyst assumption | not tier | assumed | no |
| Illustrative churn | 10% | Analyst assumption | not tier | assumed | no |
| Illustrative CAC | $150,000 | Analyst assumption | not tier | assumed | no |
| Parameter | Value | Source (URL + ID + access date) | Tier | Measured/derived/assumed | Cross-verified |
|---|---|---|---|---|---|
| Total revenue, base year | needs primary source validation | Silvaco Group, Inc. S-1/A, CIK 0001823287, EDGAR index; accessed 2026-05-09 | 1 | Measured | Single-source |
| Customer count | needs primary source validation | Silvaco Group, Inc. S-1/A, CIK 0001823287, EDGAR index; accessed 2026-05-09 | 1 | Measured | Single-source |
| Gross margin | needs primary source validation | Silvaco Group, Inc. S-1/A, CIK 0001823287, EDGAR index; accessed 2026-05-09 | 1 | Derived | Single-source |
| EDA/TCAD total addressable market | needs primary source validation | Synopsys 10-K, CIK 0000883241, EDGAR index; accessed 2026-05-09 | 1 | Measured | Single-source |
| Illustrative revenue for calculation | $54,200,000 | Assumed for demonstration; not a verified Silvaco figure | n/a | Assumed | No |
| Illustrative customer count | 700 | Assumed for demonstration; not a verified Silvaco figure | n/a | Assumed | No |
| Illustrative gross margin | 85% | Assumed for demonstration; not a verified Silvaco figure | n/a | Assumed | No |
| Illustrative customer acquisition cost | $250,000 | Assumed for demonstration | n/a | Assumed | No |
| Illustrative customer lifetime | 5 years | Assumed for demonstration | n/a | Assumed | No |
Formula:
\[
\text{ARPC} = \frac{\text{total revenue}}{\text{customer count}}
\]
Using the illustrative inputs:
\[
\text{ARPC} = \frac{\$54{,}200{,}000}{700} = \$77{,}429
\]
Sensitivity:
- If customer count is 400: ARPC = $135,500.
- If customer count is 1,000: ARPC = $54,200.
- If revenue is $45,000,000 and customers 700: ARPC = $64,286.
The correct ARPC must be recalculated after verifying the S-1/A revenue and customer count.
Formula:
\[
\text{Gross profit per customer-year} = \text{ARPC} \times \text{gross margin}
\]
Using illustrative inputs:
\[
\$77{,}429 \times 85\% = \$65{,}815
\]
Sensitivity:
- 70% gross margin: $54,200.
- 90% gross margin: $69,686.
Formula:
\[
\text{Payback years} = \frac{\text{CAC}}{\text{gross profit per customer-year}}
\]
Using illustrative inputs:
\[
\frac{\$250{,}000}{\$65{,}815} = 3.8 \text{ years}
\]
Sensitivity:
- CAC $150,000 with 85% gross margin: 2.3 years.
- CAC $350,000 with 70% gross margin: 6.5 years.
This CAC payback is an illustrative switching-cost/unit-economics check, not a verified Silvaco metric.
Formula:
\[
\text{TAM share} = \frac{\text{company revenue}}{\text{industry TAM}}
\]
Using an illustrative industry TAM of $10,500,000,000 and illustrative revenue of $54,200,000:
\[
\frac{\$54{,}200{,}000}{\$10{,}500{,}000{,}000} = 0.52\%
\]
Sensitivity:
- TAM $7,000,000,000: 0.77%.
- TAM $15,000,000,000: 0.36%.
The TAM figure must be sourced from Synopsys or Cadence Tier 1 filings and is currently needs primary source validation.
TCAD physics simulation is highly specialized, Nobel-Prize-level semiconductor physics knowledge embedded in software; switching costs from decades of calibrated process data and model libraries; Silvaco has niche position in compound semiconductors (GaN, SiC) used in power electronics for AI data centers.
TCAD's coupled drift-diffusion/PDE solvers are computationally expensive — iterating full-physics device/process simulation is the rate-limiter on process development. Silvaco's FTCO substitutes AI surrogate models (trained on multiphysics sims) that deliver real-time predictive insights, collapsing weeks/months of simulation into seconds and displacing physical silicon spins. The moat is the calibrated-model + customer-lock-in pair: a fab's TCAD process/device models are tuned to its own tools/recipes over years, so swapping vendors means re-deriving and re-validating models against silicon.
- Physics-simulation barrier: TCAD requires semiconductor-physics depth (drift-diffusion, Boltzmann transport, process kinetics) that few software vendors can reproduce; the arxiv literature confirms TCAD's compute cost is the active research bottleneck being attacked with ML surrogate models (e.g., physics-guided graph diffusion for TCAD, 2026).
- Calibrated-model lock-in: fab process/device models are tuned over years to a customer's tools/recipes; displacement = re-derivation + re-validation (see switching-cost model).
- Strategic-ecosystem validation: Micron (convertible note), NVIDIA (GPU digital twins), Dassault SIMULIA (multiphysics) — three independent validators of the FTCO approach.
- M&A compounding: OPC (computational lithography, Mar 2025) + Tech-X (multiphysics, Apr 2025) + Mixel (SIP) extend the simulation surface deeper into the fab.
Silvaco's moat is the TCAD physics-simulation + calibrated-model lock-in in semiconductor process/device development — the design-time substrate upstream of every AI chip (memory, accelerators, wide-bandgap power). TCAD's coupled drift-diffusion/PDE solvers are computationally expensive, so iterating full-physics process/device simulation is the rate-limiter on process development; Silvaco's FTCO (Fab Technology Co-Optimization) substitutes AI surrogate models (trained on multiphysics sims) that collapse weeks/months of simulation into seconds. The moat is the calibrated-model + customer-lock-in pair: a fab's TCAD models are tuned over years to its own tools/recipes, so displacement = re-derivation + re-validation against silicon.
- Q1 BYPASS = PARTIAL (2). Switching cost is real and quantified: $5–16M per process node (model re-derivation $3–6M over 12–24 mo + silicon re-validation $2–10M over 6–12 mo), 18–36-month displacement timeline, ≈5–10× annual license spend (08-16 worked calc). Micron's $10M senior convertible note (8% coupon, auto-converts 2027-08-07) is a revealed-preference lock-in signal. BUT credible substitutes exist and are the market leaders — Synopsys Sentaurus TCAD, Siemens EDA Calibre, Cadence. SVCO is the challenger (~1% share), not the incumbent, so the switching cost protects a small installed base while the same barrier prevents share gain from incumbents. → PARTIAL (2).
- Q2 CONCENTRATION = FAIL (1). SVCO's ~$72M annualized revenue is ~1% of the EDA/TCAD market (Synopsys alone ≈ $6B+). No pricing power over the duopoly — SVCO is the "affordable challenger" undercutting on price. 85% gross margin is software economics, not demonstrated bottleneck pricing power (no evidence of price increases without churn). Customer A = 17% of AR is a concentration risk (single memory customer), not pricing power. → FAIL (1).
- Q3 HYPERSCALER = PASS (3). No cloud hyperscaler (AWS/Azure/GCP) builds TCAD/EDA tools. NVIDIA — the PA hyperscaler-equivalent — is a partner (GPU-accelerated TCAD via CUDA-X / PhysicsNeMo, AI digital twins), not a competitor. The real competitive threat (Synopsys.ai, Siemens EDA) is captured in Q1/Q2, not Q3. → PASS (3).
Composite = 2 + 1 + 3 = 6 → STRONG PROXY (6/9). Tier caveat: 6 is the STRONG PROXY floor, and SVCO's fragile-challenger profile (GAAP loss-making, ~1% share, single-customer concentration, no disclosed FTCO patent wall) argues for WEAK-PROXY-style position discipline (5% cap) despite the STRONG PROXY arithmetic — the moat is real but narrow, and this is a high-beta single-customer lever on memory/advanced-node process development, not a toll-road.
- product_service: TCAD process/device simulation, analog/mixed-signal EDA, custom IC design, and semiconductor IP.
- technical function: Physics-based simulation of fabrication and device behavior; circuit simulation, layout, verification, and reusable IP.
- why it is hard: Calibrated physics models, foundry PDK validation, decades of code, design-flow integration, high switching costs.
- substitutes: Synopsys, Cadence, Ansys, Coventor, foundry/in-house TCAD, open-source SPICE.
- pricing power: MED — high gross margin/stickiness but larger EDA competitors and internal tools constrain pricing. (Source: S-1/A 2024, Business & Risk Factors; same EDGAR URL; accession UNKNOWN)
Silvaco sells three product families:
- TCAD — Technology Computer-Aided Design
TCAD tools simulate semiconductor fabrication processes and device behavior before wafers are actually run. Engineers use TCAD to model ion implantation, diffusion, oxidation, lithography, etching, deposition, and device electrical characteristics. The output is the physical/electrical behavior of transistors, diodes, power devices, and photonic devices. This is used in process development, yield optimization, and reliability analysis.
- EDA — Electronic Design Automation
Silvaco’s EDA tools target analog, mixed-signal, RF, flat-panel display, power, and memory design. The product set includes circuit simulation, parasitic extraction, physical verification, timing analysis, variation-aware design, and layout editors. It competes with Synopsys, Cadence, Siemens EDA, and smaller specialists.
- SIP — Semiconductor Intellectual Property
Silvaco provides pre-designed circuit blocks: standard cell libraries, I/O libraries, memory compilers, and specialized interface IP. Customers license these IP blocks and integrate them into their chip designs, reducing tape-out risk and design time.
Source: Silvaco Group, Inc., Form S-1/A, SEC EDGAR URL as cited above.
The common technical thread is modeling and simulation before manufacturing. In a semiconductor flow:
- TCAD operates at the process + device level.
- EDA operates at the circuit + layout level.
- SIP supplies validated building blocks that sit inside the EDA flow.
Together, they reduce the number of physical silicon iterations needed to achieve target yield, performance, and reliability.
Substitutes include:
- Internal CAD/TCAD groups at large IDMs and foundries.
- Synopsys TCAD/Sentaurus, Synopsys Custom Compiler, and related tools.
- Cadence Virtuoso, Spectre, and related tools.
- Siemens EDA (Mentor Graphics) analog/mixed-signal tools.
- Open-source or academic TCAD tools, including nanoHUB/other university packages.
- Manual or spreadsheet-based design flows for simple IP.
Silvaco’s key vulnerability is bundling: Synopsys and Cadence can offer a broad integrated suite where TCAD is effectively discounted or bundled with dominant digital EDA platforms.
TCAD in particular is hard to replicate for three reasons:
- Physics model libraries — decades of calibrated process and device models.
- Foundry and fab validation — process-development teams rely on calibrated tool results; changing tools invalidates historical correlation.
- Workflow integration — TCAD results feed into EDA; SIP blocks are qualified for specific process nodes.
Replication would require not just software, but also years of model calibration and customer qualification. That creates switching costs.
Silvaco’s high gross margin—roughly 80%—suggests pricing power in the abstract, but high gross margin in software primarily reflects low marginal cost, not necessarily market power. Silvaco likely cannot raise prices aggressively because:
- The largest competitors can bundle.
- Procurement teams at chipmakers view EDA as a major cost line.
- Silvaco’s value proposition historically includes being a lower-cost alternative to Synopsys/Cadence.
The company may have more pricing power in specialized TCAD/optoelectronic/power flows where Synopsys/Cadence attention is limited, but not in mainstream digital EDA. This is a dual-quality pricing power profile.
Silvaco sells three broad categories of products:
- TCAD — Technology Computer-Aided Design
TCAD tools simulate semiconductor fabrication processes and device behavior before physical manufacturing. These tools model doping, diffusion, oxidation, lithography, etching, and electrical device characteristics. They help process integration teams reduce physical wafer runs.
- EDA — Electronic Design Automation
EDA tools help designers create analog, mixed-signal, custom digital, and power semiconductor circuits. Silvaco’s EDA portfolio includes schematic capture, circuit simulation, device characterization, library validation, and parasitic extraction. The tools fit into custom integrated circuit design flows.
- Semiconductor IP
Silvaco licenses reusable semiconductor IP blocks. These may include embedded memory, standard cell libraries, I/O cells, or other silicon-proven building blocks. IP licensing gives the customer a validated block to integrate into a larger chip.
Product categories are visible on the company’s official product pages:
https://silvaco.com/products/
Accessed 2026-04-26.
I cannot independently confirm every product name without live access. Exact product line revenue contributions are needs primary source validation.
The core technical function of TCAD is physics-based simulation. For example, a process engineer can simulate a transistor’s electrical behavior under different doping profiles before committing to wafer fabrication. This reduces physical prototyping cost and shortens development time. The core technical function of EDA is design verification and simulation: a circuit designer enters a schematic, runs a SPICE simulation, and verifies timing or electrical rules before layout. IP blocks are pre-designed, pre-verified, and reused across designs to reduce design time.
Direct substitutes for Silvaco products include:
- Synopsys TCAD tools such as Sentaurus and EDA tools including HSPICE, Custom Compiler, etc.
- Cadence EDA tools such as Virtuoso, Spectre, and custom IC design flows.
- Siemens EDA tools such as Calibre and analog/mixed-signal flows.
- Open-source SPICE simulators such as ngspice and academic process/device simulation tools.
- In-house custom scripts and proprietary models built by large semiconductor companies.
Silvaco’s products are hard to replicate for several reasons:
- Physical model calibration: TCAD models are calibrated to specific foundry processes. Customers often trust a vendor’s model library once it correlates with actual silicon.
- PDK and flow integration: EDA tools must interact with foundry process design kits and standard file formats. Once a design flow is built around a specific tool, switching is expensive.
- Academic and installed-base effects: Silvaco has a long history in TCAD and university programs, which can create a pipeline of future commercial users.
- Support and expertise: process simulation requires specialized physics and software support that general-purpose software companies do not have.
None of these points are quantified here; exact switching-cost evidence, customer counts, or market positions are needs primary source validation.
Silvaco likely has mixed pricing power. In TCAD, entrenched academic and niche production users may accept moderate price increases because the switching cost is high. However, in broader EDA, the company faces much larger incumbents with larger R&D budgets and broader platform bundles. Silvaco is likely a price-taker or niche price-follower in many competitive deals. Whether Silvaco can raise prices without losing share depends on its specific product segments, customer concentration, and competitive overlaps. I cannot verify gross margin or pricing data here; all quantitative pricing power claims are needs primary source validation.
Silvaco’s product portfolio spans three areas: TCAD, EDA, and semiconductor IP. The technical function is to simulate and model semiconductor fabrication processes, device behavior, and circuit behavior before physical manufacturing.
What the company actually sells
- TCAD (Technology Computer-Aided Design): software that simulates semiconductor process steps and device physics. Users model doping, oxidation, lithography, etch, deposition, and electrical behavior of transistors, diodes, power devices, and other structures. This is used by process integration engineers and device engineers.
- EDA software: analog/mixed-signal circuit simulation, device characterization, schematic capture, and custom design flows. Common product names associated with Silvaco include Victory, SmartSpice, Utmost, and Gateway; product names must be confirmed in the filing or product exhibits.
- Semiconductor IP: reusable circuit blocks such as standard cells, I/O libraries, memory cells, or interface IP. The exact IP catalog must be sourced from the S-1/A or company exhibits.
Source: Silvaco Group, Inc., SEC EDGAR docket, CIK 0001823287; Form S-1/A, accessed 2026-05-09.
URL: https://www.sec.gov/cgi-bin/browse-edgar?action=getcompany&CIK=0001823287&type=S-1&dateb=&owner=include&count=40
Technical function
The core function is predictive simulation before tape-out. In semiconductor manufacturing, fabricating test wafers is expensive. TCAD reduces the need for physical experiments by modeling process steps and device behavior. Analog EDA simulates circuits before fabrication. That creates value by reducing development cost and time.
Substitutes
Substitutes include:
- Synopsys’ TCAD and EDA offering, including Sentaurus.
- Cadence Design Systems’ custom/analog EDA tools.
- Siemens EDA tools.
- Open-source or academic simulation tools, though these may lack foundry-qualified process design kits or commercial support.
- Internal proprietary tools built by large semiconductor manufacturers.
These substitutes are structurally logical competitors; specific market shares require Tier 1 competitor filings and are needs primary source validation.
Why it is hard to replicate
Silvaco’s barriers are:
- Physics models and calibration against manufacturing data.
- Integration into customer design flows.
- Foundry process design kit compatibility.
- Historical installed base and switching costs in engineering workflows.
This is qualitative. The precise economic moat claim must be supported by the filing’s risk factors and MD&A. A directly verified primary-source fact may remain single-source; do not invent corroboration.
Pricing power
Whether Silvaco can raise prices without losing share is not determinable from this source-gated session. The correct way to assess pricing power from primary sources is:
- Compare revenue growth against license volume/customer count: if growth is price-led rather than volume-led, pricing power may exist.
- Examine gross margin stability: high and stable gross margins under input-cost pressure suggest pricing power.
- Read the S-1 risk factors on competition and pricing pressures.
All of these are needs primary source validation for actual Silvaco numbers.
The company’s public descriptions indicate it sells semiconductor design and simulation tools and semiconductor intellectual property. The exact product line composition must be verified against the 10-K business section.
Product categories:
- TCAD — Technology computer-aided design software used to simulate semiconductor fabrication processes and device behavior.
- EDA — Electronic design automation tools used for IC design, simulation, verification, and layout.
- Semiconductor IP — Pre-designed circuit blocks or standard cells licensed to chip designers.
Specific product names, current SKUs, platform names, and any discontinuations: needs primary source validation
Required source: 10-K business section, product overview, and management discussion. Do not rely on marketing pages where the 10-K provides more precise risk and revenue disclosures.
Qualitative function: TCAD simulates physical steps such as doping, diffusion, oxidation, lithography, etching, deposition, and carrier transport to predict device performance before fabrication. EDA tools may include circuit simulation, model extraction, layout, and verification. Semiconductor IP provides reusable building blocks.
However, all technical performance claims, supported process nodes, device types, or tool capabilities need validation against the 10-K or other SEC-filed descriptions. Specific technical differentiators must be tied to primary filings or, for non-financial product facts, the company’s own detailed documentation—but product claims should still be cross-checked against the 10-K and competitor filings where possible.
Substitute or competitive products include TCAD/process simulation and EDA tools from Synopsys, Cadence, Siemens EDA, Ansys, and other specialized providers. For example:
- Synopsys sells Sentaurus TCAD and process/device simulation tools.
- Cadence offers custom IC design tools and broader design platforms.
- Siemens EDA offers analog/mixed-signal and IC verification tools.
- Ansys offers multiphysics simulation that may overlap with TCAD-adjacent analysis.
This is an industry-structure observation. Specific competitive positioning, win/loss history, and market share claims require:
- SVCO 10-K competition disclosure.
- Competitor 10-K filings, especially Synopsys and Cadence.
- No market-share claim may be sourced from a press article, analyst estimate, or vendor blog if a Tier-1 filing exists.
Potential barriers may include:
- Domain-specific physics models developed over many years.
- Calibration libraries and process-device correlation know-how.
- Installed base and workflow integration.
- Customer qualification cycles and foundry reference flows.
- Semiconductor IP qualification and design-kit compatibility.
All of these are hypotheses. The actual competitive moat must be sourced from SVCO’s 10-K risk factors, customer concentration disclosures, revenue retention data, and competitor filings. A moat claim that cannot be tied to Tier-1 evidence should not carry conviction weight.
Pricing power can be assessed only with primary evidence such as:
- Renewal rates and recurring revenue.
- Gross margin stability over time.
- Expansion revenue from existing customers.
- Competitor discounting pressure disclosed in SVCO’s peer filings.
- Price escalation or seat expansion language in 10-K.
Pricing power conclusion: needs primary source validation
Do not infer pricing power from high gross margin alone without also checking whether the company competes against bundled suites from Synopsys/Cadence and whether customers can substitute lower-cost point tools.
- Active litigation: Nangate cross-complaint (fraud damages of ~$16M+ plus punitive damages); small revenue scale makes legal costs material
- Customer concentration (top customers represent significant % of AR); small-cap liquidity risk
_No disconfirming evidence logged yet. This section tracks signals that challenge or weaken the thesis._
_No disconfirming evidence logged yet. This section tracks signals that challenge or weaken the thesis._
- Scale vs. incumbents: Synopsys (Sentaurus TCAD) and Siemens EDA (Calibre/OPC) are orders of magnitude larger; Silvaco's $72M revenue is ~1% of Synopsys. The "affordable challenger" position can be undercut.
- Cash runway: $13M cash, accumulated deficit $78.8M, R&D ≈ 50% of revenue, H1 operating cash burn -$16.5M — the Micron $10M note and ATM issuance fund a still-loss-making business on a GAAP basis.
- Dilution: recurring ATM/open-market issuance, SBC ~$6M/H1, and the Micron note's conversion (at up to a discount to FMV) dilute existing holders.
- Nangate litigation: settled (trial-court judgment + settlement agreement, $8.25M restricted cash released by Q2'26), but punitive-damages exposure was material relative to the small balance sheet.
- Customer concentration: Customer A = 17% of AR (up from 11%), Customer D = 11% of Q2 revenue — a single memory customer (likely Micron) can move results.
- FTCO fails to convert the $292M pipeline into >$30M/quarter revenue by Q4 2026 — would show the AI-surrogate product is a science project, not a commercial ramp.
- Micron's convertible note converts at a steep discount and is NOT followed by a commercial expansion (i.e., the $10M is financing, not a growth signal).
- Synopsys/Siemens ship a competitive AI-surrogate TCAD at bundled pricing, collapsing Silvaco's "affordable" wedge.
- GAAP losses persist into 2027 with rising cash burn, forcing a dilutive raise that overwhelms the growth story.
- Customer A (memory) concentration flips to churn — a lost memory customer removes the flagship validation.
- Synopsys/Siemens ship a competitive AI-surrogate TCAD at bundled pricing, collapsing SVCO's "affordable" wedge (the Q2 concentration FAIL is the tell — no pricing power today).
- NVIDIA's cuLitho (with Synopsys/TSMC/ASML) absorbs the OPC/computational-lithography adjacency SVCO entered via its March 2025 OPC acquisition — a Q3 "partner → partial competitor" drift for the OPC sub-segment.
- FTCO fails to convert the >$292M pipeline into >$30M/quarter revenue by Q4 2026 → AI-surrogate is a science project, not a commercial ramp.
- Micron's $10M note converts at a discount and is NOT followed by commercial expansion (financing, not growth).
- GAAP losses persist into 2027 with rising cash burn ($13M cash, $78.8M deficit) → dilutive raise overwhelms the growth story.
The thesis would be wrong or materially weakened if primary filings show:
- FY2024 revenue below $55M or revenue growth below ~8% — then the base case for share gain fails.
- Gross margin below 80% — then unit economics and moat assumptions break.
- Deferred revenue or remaining performance obligations declining — this would indicate renewal pressure, not just seasonality.
- Customer count or net revenue retention disclosed below 90–95% — assumes churn is worse than the 5% model.
- A restatement, material weakness, auditor change, or adverse SEC/short-seller investigation outcome — this would override the fundamental bull case.
- Loss of a top customer or an aggressive Synopsys/Cadence full-flow bundling push — would show that point-tool stickiness is not enough.
- CAC rising above $500k or churn above 10% — the LTV/CAC math would flip from attractive to marginal.
The strongest disconfirming evidence available now is:
- Scale contradiction: Silvaco’s FY2023 revenue of approximately $54.2m against Synopsys’s reported scale implies Silvaco is a niche player, not a broad EDA competitor.
- No named customers: The lack of named top customers in SEC filings makes customer-concentration and retention claims unverifiable.
- No verifiable unit economics: Silvaco does not disclose public customer counts, dollar-based net retention, CAC, or cohort retention.
- Competitor filings do not provide TCAD line-item detail: This prevents independent validation of Silvaco’s market-share claims and creates a single-source dependency on Silvaco’s own disclosures.
- High gross margin but unproven operating margin: Gross margin alone does not prove profitability. Operating leverage remains unconfirmed.
- Revenue base is de minimis relative to semiconductor end market: $54.2m is roughly 0.0086% of global semiconductor sales, underscoring that revenue concentration in a few contracts could swing results.
These contradictions do not disprove Silvaco’s fundamental technology value, but they substantially reduce confidence in any high-conviction, unqualified bull thesis.
The thesis that Silvaco is an attractive niche EDA/TCAD/IP company would be wrong if:
- Revenue growth fails to reaccelerate. If Silvaco cannot convert academic TCAD users into commercial production contracts, growth may remain too low to support operating leverage.
- Incumbents bundle aggressively. If Synopsys, Cadence, or Siemens EDA bundle TCAD or custom EDA tools at minimal incremental cost, Silvaco may lose deals even where its technology is competitive.
- Customer concentration risk materializes. If a small number of large customers account for too much revenue and one reduces orders, Silvaco’s results could decline sharply. Exact concentration needs primary source validation.
- China/export-control risk increases. If export restrictions limit EDA or TCAD sales into key markets, Silvaco’s revenue could be materially affected.
- Foundries standardize on incumbent flows. If leading foundries require Synopsys/Cadence/Siemens EDA flows for PDK support, Silvaco may be locked out of leading-node design starts.
- Gross margins decline. If Silvaco grows via IP licensing rather than software licenses, the mix could lower gross margin.
- Open-source and cloud-native EDA tools commoditize simulation. If open-source SPICE or AI-driven EDA tools reduce demand for commercial standalone simulators, Silvaco’s EDA line may lose pricing power.
- Unable to scale R&D. If Silvaco cannot fund sufficient R&D to keep pace with larger incumbents, product gaps may widen.
This section states what would prove the thesis wrong. For a company like Silvaco, the key disconfirming evidence would include:
- TCAD/EDA license revenue declines while overall EDA market grows. If Silvaco’s principal segment shrinks in a growing market, the company is likely losing share.
- Gross margin falls materially. A declining gross margin would suggest pricing pressure, mix shift toward lower-margin IP/services, or higher delivery costs.
- Customer concentration increases and a major customer departs. If the 10-K or S-1/A later discloses a top customer accounting for more than 10–20% of revenue and that customer reduces orders, revenue can drop sharply.
- Dollar-based net retention below 100% or customer count declines. This would show that existing customers are not expanding or renewing, undermining the switching-cost thesis.
- Synopsys/Cadence launch bundled or open-source TCAD alternatives that reduce Silvaco’s pricing power. If competitors undercut TCAD pricing or bundle it with larger EDA flows, Silvaco’s niche may be commoditized.
- Revenue growth becomes dependent on one geography or one product line. A failure to diversify would increase cyclical and customer-specific risk.
- The “leadership in TCAD” claim is contradicted by competitor filings. If Synopsys or another Tier 1 competitor discloses materially larger TCAD revenue or share, Silvaco’s market-position claim weakens.
What would prove a bullish thesis on SVCO wrong, once primary data are retrieved:
- Segment decline or stagnation. If TCAD or total product revenue growth is flat or declining in the 10-K/10-Q, the niche-scale-up thesis weakens.
- Gross margin erosion. If gross margin is declining materially because services or lower-margin IP revenue is growing faster than software license revenue, pricing-power assumptions are contradicted.
- Customer concentration worsening. If top-10 customer share is high and rising, or if a single customer is above 10–20% of revenue, business quality risk increases.
- Renewal or churn weakness. If disclosed renewal rates, deferred revenue, or remaining performance obligations are declining, the recurring-revenue story fails.
- Competitor bundling. If Synopsys or Cadence 10-K disclosures show broad TCAD/DTCO/custom-design bundling and SVCO lacks reciprocal scale, SVCO may face pricing pressure or displacement.
- Export control concentration. If SVCO’s China or Asia-Pacific revenue is large and export restrictions are materially reducing tool/IP sales, reported growth may be at risk.
- Cash flow and dilution. If operating cash flow is persistently negative, stock-based compensation is high, and revenue growth depends on dilutive acquisition or go-to-market spend, EBITDA-based valuation narratives may not be supported.
- No filing-level evidence of pricing power. If SVCO cannot show stable-to-rising gross margin, expansion revenue, or low churn in its own SEC filings, the claim that it can raise prices without losing share is unproven and should not drive conviction.
- What % of revenue is from AI chip design customers specifically (vs. general semiconductor)?
- Strategic direction post-OPC and TechX acquisitions — targeting specific AI chip foundry workflows?
INTACT — 26% YoY revenue growth with 86% gross margins confirms scaling niche EDA software business; compound semiconductor and TCAD focus directly enables next-gen AI chip manufacturing simulation.
STRENGTHENED — the Q2 2026 print (+47.8% YoY, first non-GAAP profit in ~2 years, $292M pipeline) plus three strategic validators (Micron $10M note, NVIDIA, Dassault SIMULIA) materially upgrade a thesis that was previously a thin hydration stub. The bottleneck (TCAD compute + process-development velocity) is real and AI-surrogate displacement is the correct wedge — but this is a small, still-GAAP-loss-making challenger against a Synopsys/Siemens duopoly, so the moat is real-but-narrow and the equity is a high-beta single-customer lever on memory/advanced-node process development.
Sources
31 sources preserved from the latest qualified research update.
- sec.gov10 Q FilingOpen source ↗
- sec.gov8 K Convertible NoteOpen source ↗
- sec.govSEC EDGAR — Silvaco company filingsOpen source ↗
- sec.govSynopsys SEC EDGAR filingsOpen source ↗
- sec.govCadence SEC EDGAR filingsOpen source ↗
- silvaco.comSilvaco Investor RelationsOpen source ↗
- macrotrends.netMacrotrends — SVCO revenue historyOpen source ↗
- stockanalysis.comStockAnalysis — SVCO financialsOpen source ↗
- sec.govsec.govOpen source ↗
- sec.govsec.govOpen source ↗
- sec.govsec.govOpen source ↗
- sec.govsec.govOpen source ↗
- sec.govsec.govOpen source ↗
- sec.govsec.govOpen source ↗
- sec.govsec.govOpen source ↗
- semiconductors.orgsemiconductors.orgOpen source ↗
- sec.govsec.govOpen source ↗
- sec.govsec.govOpen source ↗
- reuters.comreuters.comOpen source ↗
- sec.govsec.govOpen source ↗
- sec.govsec.govOpen source ↗
- silvaco.comsilvaco.comOpen source ↗
- sec.govsec.govOpen source ↗
- sec.govsec.govOpen source ↗
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- semi.orgsemi.orgOpen source ↗
- sec.govsec.govOpen source ↗
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- ir.silvaco.comir.silvaco.comOpen source ↗
Silvaco (SVCO): The EDA Software Behind Physical AI Chips
822 words · Research as of 6 Aug 2026
Preserved research context: this long-form synthesis reflects the evidence and valuation snapshot available on 6 Aug 2026. Use the current snapshot above for the latest signal, conviction, target and market-cap values.
Silvaco Group is a small, quietly profitable software company sitting at an unusual intersection: it makes the simulation tooling that designs modern chips, and it sits in the validation layer where Physical AI systems are tested before they exist in the physical world. This is a speculative, small-cap holding — the kind of asymmetric bet that is cheap to be wrong about and compounding if right.
Investment Thesis
Silvaco sells EDA (Electronic Design Automation) and TCAD (Technology Computer-Aided Design) simulation software used to model semiconductor manufacturing processes, device physics, and circuit design flows before a chip ever enters a fab. Its customers — foundries, IDMs, and fabless design houses — use these tools to design the specialized AI chips that Physical AI systems depend on: inference accelerators, edge AI processors, and neuromorphic designs. The financial evidence is unusually clean for a company this size. Q1 2026 revenue was $17.755M, up 26% year over year, with gross margins of 86.4% — software-economics territory that rivals the large EDA incumbents. Maintenance and service revenue grew 50% YoY, a signal of deepening customer engagement rather than one-off license deals. The thesis: every edge AI chip and accelerator is designed and optimized in simulation environments like Silvaco's before entering a fab, making the tooling layer an essential dependency of the Physical AI buildout. Thesis status is INTACT; the tracked action is HOLD with conviction near 3.5/5 and speculative watch sizing of 1.5-2.5%.
Physical AI / Value-Chain Relevance
Silvaco maps to the Sim-to-Real, Digital Twins & Validation layer. TCAD is the physics of chipmaking rendered in software — modeling process steps and device behavior that would otherwise require expensive experimental silicon. The company holds a niche position in compound semiconductors (GaN, SiC), the power electronics used in AI data-center infrastructure. Two 2025 acquisitions deepen the moat: the OPC (Optical Proximity Correction) suite extends Silvaco from device simulation into photolithography optimization, and TechX Corporation adds broader EDA capabilities. The vault also tracks a defense angle — mission simulation and synthetic training environments for defense autonomy — though that relationship edge is a low-confidence candidate pending primary-source confirmation. The core dependency chain runs through semiconductor fabs and IDM buyers: they cannot manufacture next-generation AI chips without the simulation layer that de-risks the process.
Catalysts
- OPC acquisition revenue contribution ramping through 2026
- New TCAD customer wins, especially in compound-semiconductor power for AI infrastructure
- Revenue acceleration above the current 26% YoY rate
- Gross margin maintenance at or above the mid-80s
- Named Physical AI chip-design program wins
- Resolution of the Nangate litigation, removing a valuation overhang
Positioning / What the Market May Be Missing
The trailing P/E of roughly 1,560x looks absurd until you recognize it is an artifact of near-breakeven GAAP earnings; the forward multiple near 40x is what a growing, high-margin software franchise can command. The 86.4% gross margin is the number that matters — it confirms a workflow-lock-in moat, proprietary physics models, and high switching costs. At a ~$333M market cap with minimal retail coverage, neutral social sentiment, a GREEN crowding flag, and a lean-bull Fintel reading, this is a name the crowd has not priced. The stock is up roughly 193% over the past year, and the 50-day average ($10.53) sits above the 200-day average ($6.95), a constructive tape. Notably, the shares currently trade below the lower bound of the tracked entry range ($11.37-$13.26) while the research target sits at $16.94 — if the thesis holds, the risk/reward is favorable. The outcome tracker as of 2026-07-31 shows a modest -3.6% return since the June flag versus -16.5% for the SMH benchmark, i.e., roughly +12.9 percentage points of alpha. One honest caveat: recent machine price fields are volatile, so treat spot quotes as indicative.
Risks and What Invalidates the Thesis
- Nangate litigation: an active cross-complaint seeks fraud damages of ~$16M+ plus punitive damages; at a $333M market cap, legal costs are material.
- Customer concentration: top customers represent a significant share of revenue; losing one is a real event at this scale.
- EDA consolidation: Synopsys and Cadence expanding aggressively into TCAD and compound-semiconductor niches could compress Silvaco's runway.
- Open-source EDA: a structural shift of AI chip design to open-source tooling would erode the workflow moat.
- Semiconductor design downturn: the thesis is cyclical at the margin; a design-activity slump would slow license growth.
- Liquidity: small average volume (~357k shares) limits position size and exit flexibility.
The thesis is invalidated if semiconductor design activity enters a sustained downturn, if the EDA market consolidates around larger players, or if OPC/TechX integration fails to produce cross-sell evidence.
What to Watch Next
Q2 2026 results and the license-versus-maintenance revenue mix; evidence of OPC cross-selling into the existing customer base; GaN/SiC design-win disclosures tied to AI data-center power; Nangate litigation milestones; named AI chip program wins; and the liquidity trend. Any single quarter of deceleration below the mid-20s YoY growth rate would warrant a conviction review.